10 Pages, 118 KB, Original
-0.5 to 6.0 V, speed 25=25 ns tpd CMOS programmable electrically erasable logic device
11 Pages, 384 KB, Original
CMOS Programmable Electrically Erasable Logic Device
10 Pages, 116 KB, Original
SPLD, PEEL16CV8 Family, EECMOS Process, 32 Gates, 8 Macro Cells, 8 Reg., 8 User I/Os, 5V Supply Voltage, 25 Speed Grade, 20-LDCC