Or, Call Customer Service at 1-800-548-6132 (USA Only) 16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES @ LOW COST 16-BIT 2-CHANNEL CMOS MONOLITHIC D/A CONVERTER @ SINGLE SUPPLY +5V OPERATION @ 50mW POWER DISSIPATION @ GLITCH-FREE VOLTAGE OUTPUTS @ LOW DISTORTION: -86dB max THD +N @ COMPLETE WITH REFERENCE @ SERIAL INPUT FORMAT @ SINGLE OR DUAL DAC MODE OPERATION @ PLASTIC 20-PIN SOIC PACKAGE (PCM66P) @ PLASTIC 24-PIN SOIC PACKAGE (PCM60P) PCM60P PCM66P PCM60P/66P DESCRIPTION The PCM60P/66P is a low cost, dual output 16-bit CMOS digital-to-analog converter. The PCM60P/66P features true glitch-free voltage outputs and requires only a single +5V supply. The PCM60P/66P doesnt require an extemal reference. Total power dissipation is less than 50mW max. Low maximum Total Har- monic Distortion + Noise (-86dB max; PCM60P-J, PCM66P-J) is 100% tested. Either one or two channel output modes are fully user selectable. The PCM60P/66P comes in a space-saving 24-pin plastic SOIC package. PCM60P/66P accepts a serial data input format and is compatible with other Burr- Brown PCM products such as the industry standard PCMS6P. fon AUDIO COMMUNICATIONS, DSP D/A CONV. a _... 1 Veo (45) O- Lf O Veer SOMSEL O [O Acom LADAC o14 16-Bit LCH Out LRCLK o|| conto! Vour DAC Logic Ov WOCLK O--J 4 r out CLK O-f--4 LJ Serial-to-Parallel Lo RCH Out DATA O Shift Register 1-0 Doom International Alrport Industrial Park = + Tel: (602) 746-1111 = Twa: 910-952-1111 Mailing Address: PO Box 11400 + Cable: BBRCORP + Tucson, AZ 95734 + Street Address: 6730'S. Tucson Blvd. + Tucson, AZ 85706 + Telex: 066-6491 - FAX: (602) 680-1510 + Immediate Product info: (600) 548-6132 PDS-1051B 6.2.167For immediate Assistance, Contact Your Local Salesperson SPECIFICATIONS ELECTRICAL All specifications at 25C, and +V,. = +5V unless otherwise noted. / PCM60P/E6P AND PCM60P-J/66P.J PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 16 Bits DYNAMIC RANGE . 96 3B INPUT DIGITAL INPUT TTL Compatible CMOS Logic Family Logic Level: V,, : Iq = +40HA max 42.4 45.25 v vy 4, = ~40pA max 0 08 Vv Data Format Serlal BTC Input Clock Frequency as MHz DYNAMIC CHARACTERISTICS TOTAL HARMONIC DISTORTION + N PCMB6O0P/66P: f 991Hz {0dB) {, = 176.4kHz 88 82 we f = 991HHz (-200B) f, = 176.4kHz 68 dB f = 991Hz (-60dB) f, = 176.4kHz 28 a PCMB0P-J/66P-J: f = 991Hz (0dB) f, = 176.4kHz 92 66 eB f = 991Hz (-20dB) f, = 176.4kHz 68 Bb f = 99IHz (-60db) f, = 176.4kKHz 28 B CHANNEL SEPARATION +80 +85 wB TRANSFER CHARACTERISTICS ACCURACY Gain Error Vour = 2.6 #2 +10 % Gain Mismatch Channel to Channel #1 % Bipolar Zero Error? 430 mv Gain Deitt OC to 70C 100 pprvc. Warm-up Time 1 minute IDLE CHANNEL SNR 20-20kHz with A-weighted fitter 90 dB OUTPUT ANALOG OUTPUT Output Range 2.6 Vp-p Output Impedance 2 Q Short Circuit Duration To Be Determined Settling Time Suffieient to Meet 176.4kHz THD + N Specs Glitch Energy Meets All THD + N Specs Without Extemal Output Degliitching POWER SUPPLY REQUIREMENTS +V cq, Supply Voltage +475 +5 45.25 oo Supply Current 49.5 mA Power Dissipation Vog = +5V 50 mw TEMPERATURE RANGE Specification 0 +70 Cc Operating 30 +70 C Storage -60 +100 cc NOTES: (1) Binary Two's Complement coding. (2) Ratic of (Distortion,,., + Nolse,,,,) / Signal... (3) D/A converter output frequency/signal level (on both left and tight ch is). (4) D/A sample freq y (4x 44,1kHz; 4 times oversampling per channel). (5) Offset error at bipolar zero. (6) Ratio of output at BPZ (Bipolar Zero) to the full scale ranga using 20kHz low pass filter in addition to an A-weighted fiter. The information provided herein is beBeved to be sellable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent right or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. BROWN? 6.2.168 IC Data Book Supplement, Vol. 33c fSe3)Or, Call Customer Service at 1-800-548-6132 (USA Only) MECHANICAL NOTE: Leads in tue position within 0.01" (0.25mm) R at MMC at seating plane. P Package 20-Pin Plastic SOIC PCMG6EP NOTE: Leads in true 7? position within 0.01" AAARBARAR | oznm awe JS HEBER HE EE D Pin 1 re a PU See ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION DC Supply Voltage oo AUDIO COMMUNICATIONS, DSP D/A CONV. ig PCM60P/66P Lead i ( 9, 108) +300C | 1C Data Book Supplement, Vol. 33c 6.2.169For Immediate Assistance, PCM60P PIN ASSIGNMENTS Contact Your Local Salesperson PCM66P PIN ASSIGNMENTS THEORY OF OPERATION The PCM60P/66P is a dual output, 16-bit CMOS digital-to- analog audio converter. The PCMG6OP/66P, complete with internal reference, has two glitch-free voltage outputs and requires only a single +5V power supply. Output modes using either one or two channels per DAC are user se- lectable. The PCM60P/66P accepts a serial data input format that is compatible with other Burr-Brown PCM products such as the industry standard PCMS56P. ONE DAC TWO-CHANNEL OPERATION Normally, the PCM60P/66P is operated with a continuous clock input in a two-channel output mode. This mode is selected when SDM SEL is held low (single DAC mode PIN DESCRIPTION MNEMONIC PIN DESCRIPTION MNEMONIC 1 Left/Right Clock LACLK 1 Lett/Right Clock LRCLK 2 Word Clock WOCLK 2 Word Clock WOCLK 3 Clock Input CLK 3 Glock Input CLK 4 Data input DATA 4 Data Input DATA 5 No Connection NC 5 No Connection NC 6 No Connection NC 6 Digital Common Doou 7 Digital Common Doou 7 Analog Common Accnt 8 Analog Common 8 Left Channel Vou, LCH Out 9 No Connection NC 9 Output Common Voou 10 Left Channel V,,,, L CH Out 10 Right Channel V,,,, RCH Out 1% Output Common Veo "1 Analog Supply +Vec 12 Right Channel V,, RCH Out 12 Analog Supply ve 13 +Vc, Analog Supply Voc 13 Reference Decoupie Cres 14 +Vo, Anatog Supply Vee 14 Reference Sense Ver SENSE 15 Reference Decouple Cree 15 Reference Output Veer 16 No Connection NC 16 Analog Supply wW. 17 Ver Sense Ver SENSE 7 Analog Supply aig 18 Voltage Reference Vier 18 Digital Supply +Voo 19 +V cc Analog Supply Voc 19 Single DAC Mode SDM SEL 20 +Voc Analog Supply Voc 20 LeftRight DAC Select LRDAG 24 +V,, Digital Supply +Vee 22 No Connaction NC 23 , Single DAC Mode SDM SEL 24 Left/Right DAC Select LRDAG select). Refer to the truth table shown by Table I for exact control logic relationships. Data for left and right channel output is loaded alternately into the PCM60P/66P while the control logic switches the left and right output amplifiers between the appropriate integrate and hold modes. Data word latching is controlled by WDCLK (word clock) and channel selection is made by LRCLK (left/right clock). Figure 1 shows the timing for the single DAC two-channel mode of operation. The block diagram in Figure 2 shows how a single DAC output provides switched output to both integrate and hold amplifiers. Output between left and right channels in this mode is not in phase. See Figure 3 for proper connection of the PCM60P/66P in the two-channel DAC mode. PIN FUNCTIONS SERIAL LEFT RIGHT DATA WORD CHANNEL CHANNEL SDM SEL LROAC LRCLCK WDCLK INPUT OUTPUT OUTPUT 0 x 0 0 Right Hold Hold 0 x Q 1 Right Integrate Hold 0 x 1 0 Left Hold Hold 0 x 1 1 Left Hold Integrate 1 0 0 0 Inhibited Voou Hold 1 Qo Q 1 Inhibited Veo Hold 1 0 1 0 Left Vocus Integrate 1 0 1 1 Lett Vocus Intagrate 1 1 0 0 Right Vocus Hold 1 1 0 1 Right Veens Hold 1 1 1 0 Inhibited Veons Integrate 1 1 1 1 Inhibited Voom Integrate NOTE: Positive edge of CLK (P3) latches LACLK (P1), WOCLK (P2), and DATA (P4). TABLE I. PCM60P/66P Logic Truth Table. 6.2.170 IC Data Book Supplement, Vol. 3c |Or, Call Customer Service at 1-800-548-6132 (USA Only) TWO CHANNEL PER DAC OUTPUT MODE mew UL SULT SUL. a a P1 (LACLK) | Load Right Channel Data | Load Left Channel Data L paoatay \aY2) (sXeroXefreXrralssfrelsX2) (0X9 XroXrrXreXsay rah 15} 16) P10 (LCH OUT) Hold Integrate Hold P10{LCH Vour) SSO P12 (RCH OUT) | Hold integrate NOTES: Single DAC Mode Select = 0; L/R DAC Select = X; WDCLK 50% duty cycle; Serial Data is read in MSB first with BTC coding (MSB = Bit 1). SINGLE CHANNEL PER DAC OUTPUT MODE P3 (CLK) ee UN SUL SU P2 (WDCLK) ~..D)D)r Mh hE | | eons Le P1 (LRCLK) A UCL) | Load Right DAC Data | Load Laft DAC Data | sosronce XK) LLANE) Xe KolKeteletehe) PreqncHoun) Hold ee reo oe as Right DAC P12 (RCH OUT) | Hold Integrate Left DAC rr eae a Left DAC NOTES: Single DAC Mode Select = 1; LR DAC Select = 0 (Left DAC} or 1 (Right DAC). eS AUDIO COMMUNICATIONS, DSP D/A CONV. B PCM60P/66P FIGURE 1. PCM60P/66P Timing Diagram. BUR - BROWNS IC Data Book Supplement, Vol. 33c 6.2.17]For Immediate Assistance, Contact Your Local Salesperson DATA CLK WDCLK LRCLK LRDAC Mode Control Logic SDM SEL Cree +Vcc Vcc | Veer | Vier SEN LOH Vour RCH Vour FIGURE 2. PCM60P/66P Block Diagram. PCM6OP oj t} urncik = LRDAC | 24 oj 2} wocik spMsEL | 23 o} 3} ck no | 22 o| 4 | para +Vog | 21 5 | NC +Vog | 20-4 le f | 6 | NC +Voc | 19} 4 Tt00pF 7 | Doom Veer] 18 . 4 4 8] Acow Vrer SEN $17 ~ 9} NC NC {16 te, | Fo] 10pF Of 10] LECH Ou Cerf 15 * C,- "300pF 5% y y "1 4Voc f14--# I, Cy == "B00pF 5% | oc FS ts o* 12] RCHOut = +V, [13 3] 0.1pF Polystyrene| ~ } AS Te SpF 5% Tantalum +Voc PCMGEP Mode Select rT ~] {1] LACK Mode 2 a biota J >L2] woo Mode 1 [19fo OL Input ro | al : -| 3] cK +Vog | 18 | 4] DATA +Mog | 17 [5 | Ne #Vog | 16 Cy ee | 7 | Acom Vrer SEN | 14; a ~ 8] echou = Care| 13- J E# LeHOut =~ 330pF Cape 0.1NF ~~~ 9] Vcom +Voc | 12] BOF To] RCHOM 4Mee [11 RCH Out I y 100pF Coom JL < u 3.apF Nee 45 FIGURE 3. PCM60P/66P Connection Diagram. TWO DAC TWO-CHANNEL OPERATION In phase, two-channel output can be obtained by using two PCM60P/66Ps and choosing the single DAC mode (setting SDM SEL high). With the use of a high or low input level on LRDAC (P left/right DAC select), each DAC can have its right channel output dedicated to either left or right data input with no additional input signals being required to latch the appropriate data from an alternating L/R data word input 6.2.172 stream. In the single DAC mode, the PCM60P/66Ps left channel output is disabled and held at +V,,,,._ In this mode both DACs share common inputs for DATA, CLK, WDCLK, and LRCLK, Otherwise circuit connection is the same as the two-channel DAC mode, with the exception of LRDAC whose level selects whether the single DAC will output dedicated left or right channel data. IC Data Book Supplement, Vol. 33c iOr, Call Customer Service at 1-800-548-6132 (USA Only) INTEGRATE AND HOLD OUTPUT AMPLIFIERS The PCM60P/66P incorporates integrate and hold amplifiers on each output channel. This allows a single, very fast DAC to feed both amplifiers and reduce circuit complexity. It also serves to block the output glitch from the DAC to the individual channel outputs and effectively makes the PCM60P/66P outputs glitch-free. The PCM6OP/66P is a single +5V supply device with a voltage output swing of 2.8Vp-p. The outputs swing asymmetrically around V.,, (+V,. 2.33V). See Table II for exact input/output relation- ships. Since true CMOS amplifiers are used on the PCM60P/ 66P, the load resistance on the outputs should not be less than 100kQ and the capacitive loads should not exceed 100pF. For maximum low-distortion performance, output buffer amplifiers should be considered. TABLE II. PCM60P/66P Input/Output Relationships. DISCUSSION OF SPECIFICATIONS TOTAL HARMONIC DISTORTION + NOISE The key specification for the PCM60P/66P is total harmonic distortion plus noise. Digital data words are read into the PCM60P/66P at four times the standard audio sampling frequency of 44.1kHz or 176.4kHz for each channel, such that a sine wave output of 991Hz is realized. For production testing, the output of the DAC goes to a programmabie gain amplifier to provide gain at lower signal output test levels and then through a 20kHz low pass filter before being fed DIGITAL INPUT ANALOG OUTPUT integral linearity in the DAC depending on the grade speci- Binary Two's Voltage (V) fied. The relationship between THD + N and linearity, Complement (Hex) DAC Output (V) Vou Mode however, is not such that an absolute linearity specification TFFF FS 43.5620849 for every individual output code can be guaranteed. 000 BPZ +2.1629871 8000 +S +0,7630299 25B Voou +2.6700000 IDLE CHANNEL SNR into an analog type distortion analyzer. Figure 4 shows a block diagram of the production THD + N test setup. In terms of signal measurement, THD + N is the ratio of Distortion,,,,+ Noise,,,/Signal,,,, expressed in dB. For the PCM60P/66P, THD + N is 100% tested at three different output levels using the test setup shown in Figure 4. It is significant to note that this circuit does not include any output deglitching circuitry. This means the PCM6OP/66P meets even its -60dB THD + N specification without use of external deglitchers. ABSOLUTE LINEARITY Even though absolute integral and differential linearity specs are not given for the PCM60P/66P, the extremely low THD + N performance is typically indicative of 14-bit to 15-bit Another appropriate spec for a digital audio converter is idle channel signal-to-noise ratio (idle channel SNR). This is the ratio of the noise on either DAC output at bipolar zero in relation to the full scale range of the DAC. The output of the DAC is band limited from 20Hz to 20kHz and an A- weighted filter is applied to make this measurement. OFFSET, GAIN, AND TEMPERATURE DRIFT The PCM60P/66P is specified for other important parame- ters such as channel separation and gain mismatch between output channels, And although the PCM60P/66P is primar- ily meant for use in dynamic applications, typical specs are also given for more traditional DC parameters such as gain error, bipolar zero offset error, and temperature gain drift. V. Bi PCM60P/66P AUDIO COMMUNICATIONS, DSP D/A CON Use 400Hz High-Pass Low-Pass Fier and 30kHz Distortion Meter | Programmable | Fiher LowPass Fitter _ | Stiba Soku Model~st on (Toko APO-25 Meter Settings 725 or Equivalent) dB to 600B or Equivalent) LOW-PASS FILTER A 0 ~ -20 aQ 3 -40 Binary | Digitat Code | Parallel-to-Serial DUT 3 60 Counter (EPROM) Conversion (PCM6OP/66P) -80 -100 A sib , Clock -120 Latch Enable Frequency (Hz) Sampling Rate = 44,1kHz x 4 (176.4kHz) Timing Output Frequency = 991Hz Logic FIGURE 4. THD + N Test Setup Diagram. au -BROW Ne [esEs8 IC Data Book Supplement, Vol. 33c 6.2.173 ppFor immediate Assistance, Contact Your Local Salesperson TIMING CONSIDERATIONS The data format of the PCM60P/66P is binary twos comple- ment (BTC) with the most significant bit (MSB) being first in the serial input bit stream. Table II describes the exact input data to voltage output coding relationship. Any num- ber of bits can precede the 16 bits to be loaded, as only the last 16 will be transferred to the parallel DAC register on the first positive edge of CLK (clock input) after WDCLK (word clock) has gone low. All inputs to the PCM60P/66P are TTL. level compatible. WDCLK DUTY CYCLE WDCLEK is the input signal that controls when data is loaded and how long each output is in the integrate mode. It is therefore recommended that a 50% (high) duty cycle be maintained on WDCLK. This will ensure that each output will have enough time to reach its final output value, and that the output level of each channel will be within the gain mismatch specification. Refer to Figure 1 for exact timing relationships of WDCLK to CLK and LRCLK and the outputs of the PCM60P/66P. The WDCLK can be high longer than 50%, as long as setup and hold times shown in Figure 5 are observed and the time high is roughly equiva- lent for both left and right channels. SETUP AND HOLD TIMES The individual serial data bit shifts, the serial to parallel data transfer, and left/right control are triggered on positive CLK edges. The setup time required for DATA, WDCLK, and LRCLK to be latched by the next positive going CLK is 15ns minimum. A minimum hold time of 15ns is also required after the positive going CLK edge for each data bit to be shifted into the serial input register. Refer to Figure 5 for the timing relationship of these signals. MAXIMUM CLOCK RATE The 100% tested maximum clock rate of 8.47MHz for the PCMG6O0P/66P is derived by multiplying the standard audio sample rate of 44.1kHz times eight (4x oversampling times two channels) times the standard audio word bit length of 24 (44.1kHz X 4 x 2 X 24 = 8.47MHz). Note that this clock rate accommodates a 24-bit word length, even though only 16 bits are actually being used. STOPPED-CLOCK OPERATION The PCM60P/66P is normally operated with a continuous clock input signal. If the clock is to be stopped between input data words, the last 16 bits shifted in are not actually shifted from the serial register to the latched parallel DAC register until the first clock after the one used to input bit 16 (LSB). This means the data is not shifted into the DHC latch until the start of the next 16-bit data word input, unless at least one additional clock accompanies the 16 used to serially shift in data in the first place. In either case, the setup and hold times for DATA, WDCLK, and LRCLK must still be observed. INSTALLATION The PCM60P/66P only requires a single +5V supply. The +5V supply, however, is used in deriving the intemal refer- 6.2.174 60ns min P3 (CLK) \ Y P4 (DATA) j+o| P2 (WDCLK) 15ns min Pt (LACLK) [ale 15ns min FIGURE 5. PCM60P/66P Setup and Hold Timing Diagram. ence. It is therefore very important that this supply be as clean as possible to reduce coupling of supply noise to the outputs, If a good analog supply is available at greater than +5V, a zener diode can be used to obtain a stable +5V supply. A 100F decoupling capacitor as shown in Figure 3 should be used regardless of how good the +5V supply is to maximize power supply rejection. All grounds should be connected to the analog ground plane as close to the PCM60P/ 66P as possible. . FILTER CAPACITOR REQUIREMENTS As shown in Figure 3, C,,. and V,.. SENSE should have decoupling capacitors of 0.1uF (C,) and 10uF (C,) to +V,, respectively with no special tolerance being required. To maximize channel separation between left and right chan- nels, 5% 300pF capacitors (C, and C,) between V,,,, and left and right channel outputs are required in addition to a 5% 3uF capacitor (C,) between V,,,, and +5V. The ratio of 10k to.1 is the important factor here for proper circuit operation. Placement of ali capacitors should be as close to the appro- priate pins of the PCM60P/66P as possible to reduce noise pickup from surrounding circuitry. APPLICATIONS Prebably the most popular use of the PCM60P/66P is in applications requiring single power supply operation. For example, the PCM60P/66P is ideal for automotive compact disk (CD) and digital audio tape (DAT) playback units. Fo use a more complex bipolar DAC requiring +5V supplies in the +12V application, for example, would require driving a stable floating ground and regulating the +12V to +10V. The single supply CMOS PCM60P/66P would only require a +5V zener diode to regulate its 50mW max supply. The outputs could be AC coupled to the rest of the circuit for perfectly acceptable high dynamic performance. The PCM60P/66P is ideal in any application requiring a mini- mum of additional circuitry as well as ultra-low-power CMOS performance. Of course, the PCM60P/66P is the D/A converter of choice in any application requiring very low power dissipation. Portable battery powered test and measurement equipment Tequiring very low distortion digital to analog converters would be an ideal application for the CMOS PCM60P/66P with its 50mW max power dissipation. IC Data Book Supplement, Vol. 33c [=