NB671GQ-P - Monolithic Power Systems (MPS)

NB671

24V, High Current

Synchronous Step-down Converter

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The Future of Analog IC Technology

DESCRIPTION

The NB671 is a fully integrated high frequency

synchronous rectified step-down switch mode

converter. It offers very compact solutions to

achieve 6A continuous output current and 9A

peak current over a wide input supply range

with excellent load and line regulation. The

NB671 operates at high efficiency over a wide

output current load range.

Constant-On-Time (COT) control mode

provides fast transient response and eases loop

stabilization.

Under voltage lockout is internally set as 4.6V,

An open drain power good signal indicates the

output is within its nominal voltage range.

Full protection features include OCP, OVP, and

thermal shut down.

The converter requires minimum number of

external components and is available in QFN16

(3mmx3mm) package.

FEATURES

• Wide 5V to 24V Operating Input Range

• 6A Continuous Output Current

• 9A Peak Output Current

• Low RDS(ON) Internal Power MOSFETs

• Proprietary Switching Loss Reduction

Technique

• 1% Reference Voltage

• 1.7ms Internal Soft Start

• Output Discharge

• 500kHZ Switching Frequency

• OCP, OVP, UVP Protection and Thermal

Shutdown

• Latch off Reset via EN or Power Cycle.

• Output Adjustable from 0.604V to 5.5V

APPLICATIONS

• Laptop Computer

• Tablet PC

• Networking Systems

• Personal Video Recorders

• Flat Panel Television and Monitors

• Distributed Power Systems

ll MPS parts are lead-free and adhere to the RoHS directive. For MPS green

status, please visit MPS website under Products, Quality Assurance page.

“MPS” and “The Future of Analog IC Technology” are registered trademarks o

Monolithic Power Systems, Inc.

TYPICAL APPLICATION

NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

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ORDERING INFORMATION

Part Number* Package Top Marking

NB671GQ QFN-16 (3mmx3mm) AEA

* For Tape & Reel, add suffix –Z (e.g. NB671GQ–Z)

PACKAGE REFERENCE

TOP VIEW

ABSOLUTE MAXIMUM RATINGS (1)

Supply Voltage VIN ....................................... 24V

VSW ............................................. -0.3V to 24.3V

VSW (30ns) ........................................ -3V to 28V

VSW (5ns) .......................................... -6V to 28V

VBST .................................................. VSW + 5.5V

VEN ............................................................... 12V

Enable Current IEN

(2)................................ 2.5mA

All Other Pins ............................. –0.3V to +5.5V

Continuous Power Dissipation (TA=+25°) (3)

QFN16...……………………….…..…………1.8W

Junction Temperature .............................. 150°C

Lead Temperature ................................... 260°C

Storage Temperature ............... -65°C to +150°C

Recommended Operating Conditions (4)

Supply Voltage VIN ............................. 5V to 22V

Output Voltage VOUT ................... 0.604V to 5.5V

Enable Current IEN...................................... 1mA

Operating Junction Temp. (TJ). -40°C to +125°C

Thermal Resistance (5) θJA θJC

QFN-16 (3mmx3mm) .............. 70 ...... 15 ... °C/W

Notes:

1) Exceeding these ratings may damage the device.

2) Refer to “Configuring the EN Control”.

3) The maximum allowable power dissipation is a function of the

maximum junction temperature TJ(MAX), the junction-to-

ambient thermal resistance JA, and the ambient temperature

TA. The maximum allowable continuous power dissipation a

any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-

TA)/JA. Exceeding the maximum allowable power dissipation

will cause excessive die temperature, and the regulator will go

into thermal shutdown. Internal thermal shutdown circuitry

protects the device from permanent damage.

4) The device is not guaranteed to function outside of its

operating conditions.

5) Measured on JESD51-7, 4-layer PCB.

NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

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ELECTRICAL CHARACTERISTICS

VIN = 12V, TJ = 25°C, unless otherwise noted.

Parameters Symbol Condition Min Typ Max Units

Supply Current

Supply Current (Shutdown) IIN VEN = 0V 0 1 A

Supply Current (Quiescent) IIN VEN = 2V, VFB = 0.65V 100 160 200 A

MOSFET

High-side Switch On Resistance HSRDS-ON 30 m

Low-side Switch On Resistance LSRDS-ON 15 m

Switch Leakage SWLKG V

EN = 0V, VSW = 0V 0 1 A

Current Limit

Low-side Valley Current Limit ILIMIT 8 8.5 9.5 A

Switching frequency and minimum off timer

Switching frequency FS 400 500 600 kHz

Minimum Off Time

(

)

OFF 250 300 350 ns

Over-voltage and Under-voltage Protection

OVP Threshold VOVP 125% 130% 135% VREF

OVP Delay TOVPDEL 2.5 s

UVP Threshold VUVP 55% 60% 65% VREF

UVP Delay TUVPDEL 12 s

Reference And Soft Start

Reference Voltage VREF 598 604 610 mV

Feedback Current IFB V

FB = 0.604V 10 50 nA

Soft Start Time TSS 1.5 1.7 1.95 ms

Enable And UVLO

Enable Input Low Voltage VILEN 1.15 1.25 1.35 V

Enable Hysteresis VEN-HYS 100 mV

Enable Input Current IEN VEN = 2V 5 A

VEN = 0V 0

VCC Under Voltage Lockout

Threshold Rising VCCVth 4.6 4.85 V

VCC Under Voltage Lockout

Threshold Hysteresis VCCHYS 480 mV

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, TJ = 25°C, unless otherwise noted.

Parameters Symbol Condition Min Typ Max Units

VCC Regulator

VCC Regulator VCC 4.8 5.1 5.3 V

VCC Load Regulation Icc=5mA 5 %

Power Good

FB Rising (Good) PGVth-Hi 95

%VREF

FB Falling (Fault) PGVth-Lo 85

FB Rising (Fault) PGVth-Hi 115

FB Falling (Good) PGVth-Lo 105

Power Good Lower to High Delay PGTd 0.5 ms

Power Good Sink Current

Capability VPG Sink 4mA 0.4 V

Power Good Leakage Current IPG LEAK V

PG = 3.3V 12 A

Thermal Protection

Thermal Shutdown

(

)

SD 135 150 °C

Thermal Shutdown Hysteresis

(

)

25 °C

Note:

6) Guaranteed by design.

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PIN FUNCTIONS

PIN # Name Description

1 VIN

Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The

NB671 operate from a +5V to +22V input rail. An input capacitor is needed to

decouple the input rail. Use wide PCB traces and multiple vias to make the

connection.

2 PGND Power Ground. Use wide PCB traces and multiple vias to make the connection

4 PG

Power good output, the output of this pin is an open drain signal and is high if the

output voltage is higher than 95% of the nominal voltage. There is a delay from FB 

95% to PGOOD goes high.

3, 5, 6 NC

7 VOUT

VOUT pin is used to sense the output voltage of the Buck regulator, connect this pin

to the output capacitor of the regulator directly.

8,9

Exposed

Pad 15, 16

Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is

driven up to the VIN voltage by the high-side switch during the on-time of the PWM

duty cycle. The inductor current drives the SW pin negative during the off-time. The

on-resistance of the low-side switch and the internal diode fixes the negative

voltage. Use wide and short PCB traces to make the connection. Try to minimize the

area of the SW pattern.

10 BST

Bootstrap. A capacitor connected between SW and BS pins is required to form a

floating supply across the high-side switch driver.

11 VCC

Internal 5V LDO output. The driver and control circuits are powered from this

voltage. Decouple with a minimum 1µF ceramic capacitor as close to the pin as

possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their

stable temperature characteristics.

12 FB

Feedback. An external resistor divider from the output to GND, tapped to the FB pin,

sets the output voltage. It is recommended to place the resistor divider as close to

FB pin as possible. Vias should be avoided on the FB traces. It is recommended to

set the current through FB resistors around 10uA.

13 EN

Enable pin. EN is a digital input that turns the regulator on or off. Drive EN high to

turn on the regulator, drive it low to turn it off. Connect EN with VIN through a pull-up

resistor or a resistive voltage divider for automatic startup. Do not float this pin.

14 AGND

Analog ground. The internal reference is referred to AGND. Connect the GND of the

FB divider resistor to AGND for better load regulation.

NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

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TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are tested on the evaluation board of the Design Example section.

VIN=19V, VOUT =1.05V, L=1.2µH, TJ=+25°C, unless otherwise noted.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board of the Design Example section.

VIN=19V, VOUT =1.05V, L=1.2µH, TJ=+25°C, unless otherwise noted.

NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board of the Design Example section.

VIN=19V, VOUT =1.05V, L=1.2µH, TJ=+25°C, unless otherwise noted.

NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

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BLOCK DIAGRAM

Figure 1—Functional Block Diagram

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OPERATION

PWM Operation

The NB671 is fully integrated synchronous

rectified step-down switch mode converter.

Constant-on-time (COT) control is employed to

provide fast transient response and easy loop

stabilization. At the beginning of each cycle, the

high-side MOSFET (HS-FET) is turned ON when

the feedback voltage (VFB) is below the

reference voltage (VREF), which indicates

insufficient output voltage. The ON period is

determined by both the output voltage and input

voltage to make the switching frequency fairy

constant over input voltage range.

After the ON period elapses, the HS-FET is

turned off, or becomes OFF state. It is turned ON

again when VFB drops below VREF. By

repeating operation this way, the converter

regulates the output voltage. The integrated low-

side MOSFET (LS-FET) is turned on when the

HS-FET is in its OFF state to minimize the

conduction loss. There will be a dead short

between input and GND if both HS-FET and LS-

FET are turned on at the same time. It’s called

shoot-through. In order to avoid shoot-through, a

dead-time (DT) is internally generated between

HS-FET off and LS-FET on, or LS-FET off and

HS-FET on.

An internal compensation is applied for COT

control to make a more stable operation even

when ceramic capacitors are used as output

capacitors, this internal compensation will then

improve the jitter performance without affect the

line or load regulation.

Heavy-Load Operation

Figure 2—Heavy Load Operation

When the output current is high and the inductor

current is always above zero amps, it is called

continuous-conduction-mode (CCM). The CCM

mode operation is shown in Figure 2 shown.

When VFB is below VREF, HS-MOSFET is turned

on for a fixed interval which is determined by

one- shot on-timer as equation 1 shown. When

the HS-MOSFET is turned off, the LS-MOSFET

is turned on until next period.

In CCM mode operation, the switching frequency

is fairly constant and it is called PWM mode.

Light-Load Operation

With the load decrease, the inductor current

decrease too. Once the inductor current touch

zero, the operation is transition from continuous-

conduction-mode (CCM) to discontinuous-

conduction-mode (DCM).

The light load operation is shown in Figure 3.

When VFB is below VREF, HS-MOSFET is turned

on for a fixed interval which is determined by

one- shot on-timer as equation 1 shown. When

the HS-MOSFET is turned off, the LS-MOSFET

is turned on until the inductor current reaches

zero. In DCM operation, the VFB does not reach

VREF when the inductor current is approaching

zero. The LS-FET driver turns into tri-state (high

Z) whenever the inductor current reaches zero. A

current modulator takes over the control of LS-

FET and limits the inductor current to less than -

1mA. Hence, the output capacitors discharge

slowly to GND through LS-FET. As a result, the

efficiency at light load condition is greatly

improved. At light load condition, the HS-FET is

not turned ON as frequently as at heavy load

condition. This is called skip mode.

At light load or no load condition, the output

drops very slowly and the NB671 reduces the

switching frequency naturally and then high

efficiency is achieved at light load.

Figure 3—Light Load Operation

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As the output current increases from the light

load condition, the time period within which the

current modulator regulates becomes shorter.

The HS-FET is turned ON more frequently.

Hence, the switching frequency increases

correspondingly. The output current reaches the

critical level when the current modulator time is

zero. The critical level of the output current is

determined as follows:

IN OUT OUT

OUT SW IN

(V V ) V

I2LF V

−×

=×× × (1)

It turns into PWM mode once the output current

exceeds the critical level. After that, the switching

frequency stays fairly constant over the output

current range.

Jitter and FB Ramp Slope

Jitter occurs in both PWM and skip modes when

noise in the VFB ripple propagates a delay to the

HS-FET driver, as shown in Figures 4 and 5.

Jitter can affect system stability, with noise

immunity proportional to the steepness of VFB’s

downward slope. However, VFB ripple does not

directly affect noise immunity.

VREF

VFB

HS Driver

NOISE

J itter

VS L O PE1

Figure 4—Jitter in PWM Mode

HS D river

Jitter

REF

SLOPE2

NOISE

Figure 5—Jitter in Skip Mode

Operating without external ramp

The traditional constant-on-time control scheme

is intrinsically unstable if output capacitor’s ESR

is not large enough as an effective current-sense

resistor. Ceramic capacitors usually can not be

used as output capacitor.

To realize the stability, the ESR value should be

chosen as follow:

SW ON

ESR

OUT

0.7 2

×π

≥ (2)

TSW is the switching period.

The NB671 has built in internal ramp

compensation to make sure the system is stable

even without the help of output capacitor’s ESR;

and thus the pure ceramic capacitor solution can

be applicant. The pure ceramic capacitor solution

can significantly reduce the output ripple, total

BOM cost and the board area.

Figure 6 shows a typical output circuit in PWM

mode without an external ramp circuit. Turn to

application information section for design steps

without external compensation.

ESR

CAP

Figure 6—Simplified Circuit in PWM Mode

without External Ramp Compensation

When using a large-ESR capacitor on the output,

add a ceramic capacitor with a value of 10uF or

less to in parallel to minimize the effect of ESL.

Operating with external ramp compensation

The NB671 is usually able to support ceramic

output capacitors without external ramp, however,

in some of the cases, the internal ramp may not

be enough to stabilize the system, and external

ramp compensation is needed. Skip to

application information section for design steps

with external ramp compensation.

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Figure 7—Simplified Circuit in PWM Mode

with External Ramp Compensation

Figure 7 shows a simplified external ramp

compensation (R4 and C4) for PWM mode, with

HS-FET off. Chose R1, R2, R9 and C4 of the

external ramp to meet the following condition:

SW 4 1 2

11 R

2F C 5RR

⎛⎞

<× +

⎜⎟

π× × +

⎝⎠

(3)

Where:

R4 C4 FB C4

IIII=+≈ (4)

And the Vramp on the VFB can then be estimated

as:

IN OUT 12

RAMP ON

44 129

VV R//R

RC R//RR

−

=××

×+

(5)

The downward slope of the VFB ripple then

follows

−

OUT

RAMP

SLOPE1

off 4 4

VTRC

(6)

As can be seen from equation 6, if there is

instability in PWM mode, we can reduce either

R4 or C4. If C4 can not be reduced further due to

limitation from equation 3, then we can only

reduce R4. For a stable PWM operation, the

Vslope1 should be design follow equation 7.

SW ON -3

ESR OUT

slope1 OUT

OUT SW on

+-RC Io 10

0.7 2

-V V +

2LC T -T

≥×× (7)

Io is the load current.

In skip mode, the downward slope of the VFB

ripple is the same whether the external ramp is

used or not. Figure 8 shows the simplified circuit

of the skip mode when both the HS-FET and LS-

FET are off.

Figure 8—Simplified Circuit in skip Mode

The downward slope of the VFB ripple in skip

mode can be determined as follow:

()

REF

SLOPE2

12 OUT

V(R R //Ro) C

−

=+×

(8)

Where Ro is the equivalent load resistor.

As described in Figure 5, VSLOPE2 in the skip

mode is lower than that is in the PWM mode, so

it is reasonable that the jitter in the skip mode is

larger. If one wants a system with less jitter

during light load condition, the values of the VFB

resistors should not be too big, however, that will

decrease the light load efficiency.

Configuring the EN Control

EN is used to enable or disable the whole chip.

Pull En high to turn on the regulator and pull EN

low to turn it off. Do not float the pin.

For automatic start-up the EN pin can be pulled

up to input voltage through a resistive voltage

divider. Choose the values of the pull-up resistor

(Rup from Vin pin to EN pin) and the pull-down

resistor (Rdown from EN pin to GND) to

determine the automatic start-up voltage:

up down

IN START

down

(R R )

V1.25 (V)

−

=× (9)

For example, for Rup=150k and

Rdown=51k,the −IN START

Vis set at 4.93V.

To avoid noise, a 10nF ceramic capacitor from

EN to GND is recommended.

There is an internal Zener diode on the EN pin,

which clamps the EN pin voltage to prevent it

from running away. The maximum pull up current

assuming a worst case 12V internal Zener clamp

should be less than 1mA.

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Therefore, when EN is driven by an external logic

signal, the EN voltage should be lower than 12V;

when EN is connected with VIN through a pull-up

resistor or a resistive voltage divider, the

resistance selection should ensure the maximum

pull up current less than 1mA.

If using a resistive voltage divider and VIN higher

than 12V, the allowed minimum pull-up resistor

Rup should meet the following equation:

up down

V -12V 12V

-=1mA

RR (10)

Especially, just using the pull-up resistor Rup(the

pull-down resistor is not connected), the

IN-START

Vis determined by input UVLO, and the

minimum resistor value is:

V-12V

R= (W)

1mA (11)

A typical pull-up resistor is 499k.

Soft Start

The NB671 employs soft start (SS) mechanism

to ensure smooth output during power-up. When

the EN pin becomes high, the internal reference

voltage ramps up gradually; hence, the output

voltage ramps up smoothly, as well. Once the

reference voltage reaches the target value, the

soft start finishes and it enters into steady state

operation.

If the output is pre-biased to a certain voltage

during startup, the IC will disable the switching of

both high-side and low-side switches until the

voltage on the internal reference exceeds the

sensed output voltage at the FB node.

Power Good (PGOOD)

The NB671 has power-good (PGOOD) output

used to indicate whether the output voltage of the

Buck regulator is ready or not. The PGOOD pin

is the open drain of a MOSFET. It should be

connected to VCC or other voltage source through

a resistor (e.g. 100k). After the input voltage is

applied, the MOSFET is turned on so that the

PGOOD pin is pulled to GND before SS is ready.

After FB voltage reaches 95% of REF voltage,

the PGOOD pin is pulled high after a delay. The

PGOOD delay time is 0.5ms.

When the FB voltage drops to 85% of REF

voltage, the PGOOD pin will be pulled low.

Over Current Protection

NB671 has cycle-by-cycle over current limiting

control. The current-limit circuit employs a

"valley" current-sensing algorithm. The part uses

the Rds(on) of the low side MOSFET as a

current-sensing element. If the magnitude of the

current-sense signal is above the current-limit

threshold, the PWM is not allowed to initiate a

new cycle.

The trip level is fixed internally. The inductor

current is monitored by the voltage between GND

pin and SW pin. GND is used as the positive

current sensing node so that GND should be

connected to the source terminal of the bottom

MOSFET.

Since the comparison is done during the high

side MOSFET OFF and low side MOSFET ON

state, the OC trip level sets the valley level of the

inductor current. Thus, the load current at over-

current threshold, IOC, can be calculated as

follows:

inductor

I I _ limit 2 (12)

In an over-current condition, the current to the

load exceeds the current to the output capacitor;

thus the output voltage tends to fall off.

Eventually, it will end up with crossing the under

voltage protection threshold and shutdown.And

fault latching can be reset by EN going low or

Power-cycling of VIN.

Over/Under-Voltage Protection (OVP/UVP)

NB671 monitors a resistor divided feedback

voltage to detect over and under voltage. When

the feedback voltage becomes higher than 115%

of the target voltage, the controller will enter

Dynamic Regulation Period. During this period,

the LS will off when the LS current goes to -1A,

this will then discharge the output and try to keep

it within the normal range. If the dynamic

regulation can not limit the increasing of the Vo,

once the feedback voltage becomes higher than

130% of the feedback voltage, the OVP

comparator output goes high and the circuit

latches as the high-side MOSFET driver OFF

and the low-side MOSFET turns on acting as an -

1A current source.

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When the feedback voltage becomes lower than

60% of the target voltage, the UVP comparator

output goes high if the UV still occurs after typical

12s delay; then the fault latch will be triggered---

latches HS off and LS on; the LS FET keeps on

until the inductor current goes zero. Also fault

latching can be reset by EN going low or Power-

cycling of VIN.

UVLO Protection

The NB671 has under-voltage lock-out protection

(UVLO). When the VCC voltage is higher than

the UVLO rising threshold voltage, the part will

be powered up. It shuts off when the VIN voltage

is lower than the UVLO falling threshold voltage.

This is non-latch protection. The part is disabled

when the VCC voltage falls below 4.6V. Besides

fault latching can be reset by EN going low or

Power-cycling of VIN. If an application requires a

higher under-voltage lockout (UVLO), use the EN

pin as shown in Figure 9 to adjust the input

voltage UVLO by using two external resistors. It

is recommended to use the enable resistors to

set the UVLO falling threshold (VSTOP) above

4.6V. The rising threshold (VSTART) should be

set to provide enough hysteresis to allow for any

input supply variations.

Figure 9—Adjustable UVLO

Thermal Shutdown

Thermal shutdown is employed in the NB671.

The junction temperature of the IC is internally

monitored. If the junction temperature exceeds

the threshold value (typical 150ºC), the converter

shuts off. This is a non-latch protection. There is

about 25ºC hysteresis. Once the junction

temperature drops to about 125ºC, it initiates a

SS.

Output Discharge

NB671 discharges the output when EN is low, or

the controller is turned off by the protection

functions (UVP & OCP, OCP, OVP, UVLO, and

thermal shutdown). The part discharges outputs

using an internal 6 MOSFET which is

connected to VOUT and GND. The external low-

side MOSFET is not turned on for the output

discharge operation to avoid the possibility of

causing negative voltage at the output.

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APPLICATION INFORMATION

Setting the Output Voltage---without external

compensation

For applications that electrolytic capacitor or POS

capacitor with a controlled output of ESR is set

as output capacitors, or the internal

compensation is enough for a stable operation

when ceramic capacitors is used, then the

external compensation is not need.. The output

voltage is set by feedback resistors R1 and R2.

As Figure 10 shows.

Figure10—Simplified Circuit of POS Capacitor

First, choose a value for R2. R2 should be

chosen reasonably, a small R2 will lead to

considerable quiescent current loss while too

large R2 makes the FB noise sensitive. It is

recommended to choose a value within 5k-

100k for R2,.Typically, set the current through

R2 between 5-30uA will make a good balance

between system stability and also the no load

loss. Then R1 is determined as follow with the

output ripple considered:

OUT OUT REF

REF

VVV

−Δ −

=⋅

(13)

OUT

VΔ is the output ripple.

Setting the Output Voltage---with external

compensation

Figure11—Simplified Circuit of Ceramic

Capacitor

If the system is not stable enough when low ESR

ceramic capacitor is used in the output, an

external voltage ramp should be added to FB

through resistor R4 and capacitor C4.The output

voltage is influenced by ramp voltage VRAMP

besides R divider as shown in Figure 11. The

VRAMP can be calculated as shown in equation 7.

R2 should be chosen reasonably, a small R2 will

lead to considerable quiescent current loss while

too large R2 makes the FB noise sensitive. It is

recommended to choose a value within 5k-

100k for R2.Typically, set the current through

R2 between 5-30uA will make a good balance

between system stability and also the no load

loss. And the value of R1 then is determined as

follow:

FB(AVG) 2

OUT FB(AVG) 4 9

R= VR

(V -V ) R +R

(14)

The VFB(AVG) is the average value on the FB,

VFB(AVG) varies with the Vin, Vo, and load

condition, etc., its value on the skip mode would

be lower than that of the PWM mode, which

means the load regulation is strictly related to the

VFB(AVG). Also the line regulation is related to the

VFB(AVG). If one wants to gets a better load or line

regulation, a lower Vramp is suggested, as long

as the criterion shown in equation 8 can be met.

For PWM operation, VFB(AVG) value can be

deduced from the equation below.

FB( AVG) REF RAMP

12 9

R//R

VVV

2R//RR

=+ × + (15)

Usually, R9 is set to 0, and it can also be set

following equation 14 for a better noise immunity.

It should also set to be 5 times smaller than

R1//R2 to minimize its influence on Vramp.

4SW

R2C2F

=π× × (16)

Using equation 13 to calculate the R1 can be

complicated. To simplify the calculation, a DC-

blocking capacitor Cdc can be added to filter the

DC influence from R4 and R9. Figure 12 shows

a simplified circuit with external ramp

compensation and a DC-blocking capacitor. With

this capacitor, R1 can easily be obtained by

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using the simplified equation for PWM mode

operation:

−−

OUT REF RAMP

REF RAMP

(V V V )

(17)

Cdc is suggested to be at least 10 times larger

than C4 for better DC blocking performance, and

should also not larger than 0.47uF considering

start up performance. In case one wants to use

larger Cdc for a better FB noise immunity,

combined with reduced R1 and R2 to limit the

Cdc in a reasonable value without affecting the

system start up. Be noted that even when the

Cdc is applied, the load and line regulation are

still Vramp related.

Ceramic

VoL

Cdc

R4 C4

Figure12—Simplified Circuit of Ceramic

Capacitor with DC blocking capacitor

Input Capacitor

The input current to the step-down converter is

discontinuous and therefore requires a capacitor

to supply the AC current to the step-down

converter while maintaining the DC input voltage.

Ceramic capacitors are recommended for best

performance and should be placed as close to

the VIN pin as possible. Capacitors with X5R and

X7R ceramic dielectrics are recommended

because they are fairly stable with temperature

fluctuations.

The capacitors must also have a ripple current

rating greater than the maximum input ripple

current of the converter. The input ripple current

can be estimated as follows:

OUT OUT

CIN OUT

IN IN

II (1 )

=× ×− (18)

The worst-case condition occurs at VIN = 2VOUT,

where:

OUT

CIN

= (19)

For simplification, choose the input capacitor with

an RMS current rating greater than half of the

maximum load current.

The input capacitance value determines the input

voltage ripple of the converter. If there is an input

voltage ripple requirement in the system, choose

the input capacitor that meets the specification.

The input voltage ripple can be estimated as

follows:

OUT OUT OUT

SW IN IN IN

IV V

V(1)

FC V V

Δ= × ×−

× (20)

Under worst-case conditions where VIN = 2VOUT:

OUT

SW IN

V4F C

Δ=× × (21)

Output Capacitor

The output capacitor is required to maintain the

DC output voltage. Ceramic or POSCAP

capacitors are recommended. The output voltage

ripple can be estimated as:

OUT OUT

OUT ESR

SW IN SW OUT

VV 1

V(1)(R )

FL V 8FC

Δ= ×− × +

×××

(22)

In the case of ceramic capacitors, the impedance

at the switching frequency is dominated by the

capacitance. The output voltage ripple is mainly

caused by the capacitance. For simplification, the

output voltage ripple can be estimated as:

OUT OUT

OUT 2

SW OUT IN

V(1)

8F LC V

Δ= ×−

××× (23)

The output voltage ripple caused by ESR is very

small. Therefore, an external ramp is needed to

stabilize the system. The external ramp can be

generated through resistor R4 and capacitor C4.

In the case of POSCAP capacitors, the ESR

dominates the impedance at the switching

frequency. The ramp voltage generated from the

ESR is high enough to stabilize the system.

Therefore, an external ramp is not needed. A

minimum ESR value around 12m is required to

ensure stable operation of the converter. For

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simplification, the output ripple can be

approximated as:

OUT OUT

OUT ESR

SW IN

V(1)R

FL V

Δ= ×− ×

× (24)

Maximum output capacitor limitation should be

also considered in design application. NB671 has

an around 1.7ms soft-start time period. If the

output capacitor value is too high, the output

voltage can’t reach the design value during the

soft-start time, and then it will fail to regulate. The

maximum output capacitor value Co_max can be

limited approximately by:

O _ MAX LIM _ AVG OUT ss OUT

C(I I)T/V=−× (25)

Where, ILIM_AVG is the average start-up current

during soft-start period. Tss is the soft-start time.

Inductor

The inductor is necessary to supply constant

current to the output load while being driven by

the switched input voltage. A larger-value

inductor will result in less ripple current that will

result in lower output ripple voltage. However, a

larger-value inductor will have a larger physical

footprint, higher series resistance, and/or lower

saturation current. A good rule for determining

the inductance value is to design the peak-to-

peak ripple current in the inductor to be in the

range of 30% to 40% of the maximum output

current, and that the peak inductor current is

below the maximum switch current limit. The

inductance value can be calculated by:

OUT OUT

SW L IN

L(1)

FI V

=×−

×Δ (26)

Where IL is the peak-to-peak inductor ripple

current.

The inductor should not saturate under the

maximum inductor peak current, where the peak

inductor current can be calculated by:

OUT OUT

LP OUT

SW IN

II (1 )

2F L V

=+ ×−

× (27)

PCB Layout Guide

1. The high current paths (GND, IN, and SW)

should be placed very close to the device

with short, direct and wide traces.

2. Put the input capacitors as close to the IN

and GND pins as possible.

3. Put the decoupling capacitor as close to the

VCC and GND pins as possible. Place the

Cap close to AGND if the distance is long.

And place >3 Vias if via is required to reduce

the leakage inductance.

4. Keep the switching node SW short and away

from the feedback network.

5. The external feedback resistors should be

placed next to the FB pin. Make sure that

there is no via on the FB trace.

6. Keep the BST voltage path (BST, C3, and

SW) as short as possible.

7. Keep the IN and GND pads connected with

large copper and use at least two layers for

IN and GND trace to achieve better thermal

performance. Also, add several Vias with

10mil_drill/18mil_copper_width close to the

IN and GND pads to help on thermal

dissipation.

8. Four-layer layout is strongly recommended to

achieve better thermal performance.

Note:

Please refer to the PCB Layout Application Note

for more details.

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Figure 13—Recommend Layout

Recommend Design Example

Two design examples are provided below when

the ceramic capacitors are applied:

Table 1—Design Example

OUT

(V)

Cout

(F)

(μH)

(Ω)

(F)

(Ω)

(kΩ)

1.05 22x2+47 1.2 1M 220p 499 63.4 82

5.0 22x3 2 1M 220p 499 150 18

The detailed application schematic is shown in

Figure 14 when low ESR caps are used. The

typical performance and circuit waveforms have

been shown in the Typical Performance

Characteristics section. For more possible

applications of this device, please refer to related

Evaluation Board Data Sheets.

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TYPICAL APPLICATION

Figure 14 — Typical Application Circuit with Low ESR Ceramic Output Capacitor

VIN=6.5-22V, VOUT=1.05V, IOUT=6A

Figure 15 — Typical Application Circuit with Low ESR Ceramic Output Capacitor

VIN=7-22V, VOUT=5V, IOUT=6A

NB671, 24V, HIGH CURRENT SYNCHRONOUS STEP-DOWN CONVERTER

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third

party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not

assume any legal responsibility for any said applications.

NB671 Rev. 1.02 www.MonolithicPower.com 20

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PACKAGE INFORMATION

QFN16 (3X3mm)

SIDE VIEW

BOTTOM VIEW

NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) EXPOSED PADDLE SIZE DOES NOT INCLUDE

MOLD FLASH.

3) LEAD COPLANARITY SHALL BE 0.10

MILLIMETERS MAX.

4) JEDEC REFERENCE IS MO-220.

5) DRAWING IS NOT TO SCALE.

PIN 1 ID

MARKING

TOP VIEW

PIN 1 ID

INDEX AREA

RECOMMENDED LAND PATTERN

0.10x45°

PIN 1 ID

0.10x45癟YP.

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