www.lansdale.comPage 1 of 35 Issue A
ML145151
ML145152
ML145155
ML145156
ML145157
ML145158
PLL Frequency Synthesizer Family - CMOS
The devices described in this document are typically used as low–power, phase–locked loop frequency
synthesizers. When combined with an external low–pass filter and voltage–controlled oscillator, these
devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the
device's frequency limit. For higher VCO frequency operation, a down mixer or a prescaler can be used
between the VCO and the synthesizer IC.
These frequency synthesizer chips can be found in the following and other applications:
CATV TV Tuning
AM/FM Radios Scanning Receivers
Two–Way Radios Amateur Radio
CONTENTS
Page
DEVICE DETAIL SHEETS
ML145151 Parallel–Input, Single–Modulus ...........................................................................................2
ML145152 Parallel–Input, Dual–Modulus..............................................................................................5
ML145155 Serial–Input, Single–Modulus ..............................................................................................9
ML145156 Serial–Input, Dual–Modulus...............................................................................................13
ML145157 Serial–Input, Single–Modulus ............................................................................................17
ML145158 Serial–Input, Dual–Modulus...............................................................................................20
FAMILY CHARACTERISTICS
Maximum Ratings..................................................................................................................................23
DC Electrical Characteristics.................................................................................................................23
AC Electrical Characteristics .................................................................................................................25
Timing Requirements.............................................................................................................................26
Frequency Characteristics ......................................................................................................................27
Phase Detector/Lock Detector Output Waveforms................................................................................27
DESIGN CONSIDERATIONS
Phase–Locked Loop – Low–Pass Filter Design ....................................................................................28
Crystal Oscillator Considerations ..........................................................................................................29
Dual–Modulus Prescaling......................................................................................................................30
R÷
÷÷
÷
OSC
CONTROL LOGIC
N
A
φ
P/P + 1VCO
OUTPUT
FREQUENCY
EXTERNAL
COMPONENTS
www.lansdale.comPage 2 of 35 Issue A
ML145151
Parallel-Input PLL
Frequency Synthesizer
Interfaces with Single–Modulus Prescalers
Legacy Device: Motorola/Freescale MC145151
The ML145151 is programmed by 14 parallel–input data
lines for the N counter and three input lines for the R counter.
The device features consist of a reference oscillator, selec-
table–reference divider, digital–phase detector, and 14–bit
programmable divide–by–N counter.
• Operating Temperature Range: TA = – 40 to 85°C
• Low Power Consumption Through Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation
• Lock Detect Signal
• ÷ N Counter Output Available
• Single Modulus/Parallel Programming
• 8 User–Selectable ÷ R Values: 8, 128, 256, 512, 1024,
2048, 2410, 8192
• ÷ N Range = 3 to 16383
• “Linearized” Digital Phase Detector Enhances Transfer
Function Linearity
• Two Error Signal Options: Single–Ended (Three–State)
or Double–Ended
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates
P DIP 28 = YP
PLASTIC DIP
CASE 710
SO 28W = -6P
SOG PACKAGE
CASE 751F
1
28
1
28
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
P DIP 28 MC145151P2 ML145151YP
SO 28W MC145151DW2 ML145151-6P
LANSDALEPACKAGE
5
4
3
2
1
10
9
8
7
6
11
12
13
14
20
21
22
23
24
25
26
19
27
28
18
17
16
15
RA2
PDout
VDD
VSS
fin
N0
φ
R
RA0
N3
N2
N1
RA1
φ
V
fV
N10
N11
OSCout
OSCin
LD
N5
N6
N7
N4
N9
N12
N13
N8
T/R
PIN ASSIGNMENT
www.lansdale.comPage 3 of 35 Issue A
LANSDALE Semiconductor, Inc.
ML145151
14 x 8 ROM REFERENCE DECODER
14–BIT
÷
N COUNTER
φ
V
ML145151 BLOCK DIAGRAM
φ
R
14–BIT
÷
R COUNTER
TRANSMIT OFFSET ADDER
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT LD
PDout
RA2
fin
VDD
OSCin
OSCout
T/R
14
14
fV
N13N11 N9N7N6 N4 N2N0
NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 1)
Input to the ÷N portion of the synthesizer. fin is typically
derived from loop VCO and is AC coupled into the device. For
larger amplitude signals (standard CMOS logic levels) DC
coupling may be used.
RA0 – RA2
Reference Address Inputs (Pins 5, 6, 7)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as defined
by the table below.
Pull–up resistors ensure that inputs left open remain at a
logic 1 and require only a SPST switch to alter data to the zero
state.
N0 – N11
N Counter Programming Inputs (Pins 11 – 20, 22 – 25)
These inputs provide the data that is preset into the ÷ N
counter when it reaches the count of zero. N0 is the least sig-
nificant and N13 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only
an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at
the N inputs. This is normally used for offsetting the VCO fre-
quency by an amount equal to the IF frequency of the trans-
ceiver. This offset is fixed at 856 when T/R is low and gives no
offset when T/R is high. A pull–up resistor ensures that no
connection will appear as a logic 1 causing no offset addition.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally generated refer-
ence signal. This signal is typically AC coupled to OSCin, but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
OUTPUT PINS
PDout
Phase Detector A Output (Pin 4)
Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this pur-
pose (see ΦV and ΦR).
Frequency fV> fRor fVLeading: Negative Pulses
Frequency fV< fRor fVLagging: Positive Pulses
Frequency fV= fRand Phase Coincidence: High–Imped-
ance State
Reference Address Code Total
Divide
RA2 RA1 RA0
Di
v
id
e
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
128
256
512
1024
2048
2410
8192
www.lansdale.comPage 4 of 35 Issue A
φR,φV
Phase Detector B Outputs (Pins 8, 9)
These phase detector outputs can be combined externally for
a loop–error signal. A single–ended output is also available for
this purpose (see PDout).
If frequency fVis greater than fRor if the phase of fVis
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fVis less than fRor if the phase of fVis
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV= fRand both are in phase, then both
φV and φR remain high except for a small minimum time peri-
od when both pulse low in phase.
fV
N Counter Output (Pin 10)
This is the buffered output of the ÷ N counter that is inter-
nally connected to the phase detector input. With this output
available, the ÷ N counter can be used independently.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (fR, fVof same
phase and frequency). Pulses low when loop is out of lock.
POWER SUPPLY
VDD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually-
ground.
LANSDALE Semiconductor, Inc.
ML145151
TYPICAL APPLICATIONS
Figure 1. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz
0 1 1 1 0 0 0 1 0 0 0 = 5 MHz
1 0 1 0 1 1 1 1 1 0 0 = 5.5 MHz
5 – 5.5 MHz
VOLTAGE
CONTROLLED
OSCILLATOR
NCNC
PDout
RA0RA1RA2
N13N0N1N2N3N4N5N6N7N8N9N10N11N12
ML145151
fin
OSCout
OSCin
2.048 MHz
Figure 2. Synthesizer for Land Mobile Radio UHF Bands
NOTES:
1. fR = 4.1667 kHz; ÷ R = 2410; 21.4 MHz low side injection during receive.
2. Frequency values shown are for the 440 – 470 MHz band. Similar implementation applies to the 406 – 440 MHz band.
For 470 – 512 MHz, consider reference oscillator frequency X9 for mixer injection signal (90.3750 MHz).
60.2500 MHz
“0”“1”“1” CHOICE OF
DETECTOR
ERROR
SIGNALS
LOCK DETECT SIGNAL
T: 13.0833 – 18.0833 MHz
R: 9.5167 – 14.5167 MHz
T: 73.3333 – 78.3333 MHz
R: 69.7667 – 74.7667 MHz
X6VCO
LOOP
FILTER
DOWN
MIXER
X6
T/R
VSS
VDD
CHANNEL PROGRAMMING
÷
N = 2284 TO 3484
TRANSMIT
(ADDS 856 TO
÷
N VALUE)
RECEIVE
REF. OSC.
10.0417 MHz
(ON–CHIP OSC.
OPTIONAL)
“1”“0”“0”
fV
LDRA0RA1RA2
OSCin
OSCout
ML145151
+ V
TRANSMIT: 440.0 – 470.0 MHz
RECEIVE: 418.6 – 448.6 MHz
(25 kHz STEPS)
PDout
φ
R
fV
fin
ML145151 Data Sheet Continued on Page 23
www.lansdale.comPage 5 of 35 Issue A
ML145152
Parallel-Input PLL
Frequency Synthesizer
Interfaces with Dual–Modulus Prescalers
Legacy Device: Motorola/Freescale MC145152
The ML145152 is programmed by sixteen parallel inputs
for the N and A counters and three input lines for the R
counter. The device features consist of a reference oscillator,
selectable–reference divider, two–output phase detector,
10–bit programmable divide–by–N counter, and 6–bit pro-
grammable ÷ A counter.
• Operating Temperature Range: TA= – 40 to 85°C
• Low Power Consumption Through Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation
• Lock Detect Signal
• Dual Modulus/Parallel Programming
• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 512,
1024, 1160, 2048
• ÷ N Range = 3 to 1023, ÷ A Range = 0 to 63
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates
• See Application Note AN980
P DIP 28 = YP
PLASTIC DIP
CASE 710
SO 28W = -6P
SOG PACKAGE
CASE 751F
1
28
1
28
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
P DIP 28 MC145152P2 ML145152YP
SO 28W MC145152DW2 ML145152-6P
LANSDALEPACKAGE
5
4
3
2
1
10
9
8
7
6
11
12
13
14
20
21
22
23
24
25
26
19
27
28
18
17
16
15
φ
R
RA0
VDD
VSS
fin
N0
φ
V
RA1
N3
N2
N1
RA2
MC
A5
A3
A4
OSCout
OSCin
LD
N5
N6
N7
N4
N9
A2
A0
N8
A1
PIN ASSIGNMENT
www.lansdale.comPage 6 of 35 Issue A
LANSDALE Semiconductor, Inc.
ML145152
12 x 8 ROM REFERENCE DECODER
φ
V
ML145152 BLOCK DIAGRAM
φ
R
12–BIT
÷
R COUNTER
PHASE
DETECTOR
LOCK
DETECT LD
fin
OSCin
OSCout12
N0 N2 N4 N5 N7 N9
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
10–BIT
÷
N COUNTER
CONTROL
LOGIC
MC
6–BIT
÷
A COUNTER
A5 A3A2 A0
RA2
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 1)
Input to the positive edge triggered ÷ N and ÷ A counters.
fin is typically derived from a dual–modulus prescaler and is
AC coupled into the device. For larger amplitude signals (stan-
dard CMOS logic levels) DC coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider. The total
reference divide values are as follows:
N0 – N9
N Counter Programming Inputs (Pins 11 – 20)
The N inputs provide the data that is preset into the ÷ N
counter when it reaches the count of 0. N0 is the least signifi-
cant digit and N9 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only a
SPST switch to alter data to the zero state.
A0 – A5
A Counter Programming Inputs(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of fin that
require a logic 0 on the MC output (see Dual–Modulus Pres-
caling section). The A inputs all have internal pull–up resis-
tors that ensure that inputs left open will remain at a logic 1.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally generated refer-
ence signal. This signal is typically AC coupled to OSCin, but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
OUTPUT PINS
φR,φV
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally for
a loop–error signal.
If the frequency fVis greater than fRor if the phase of fVis
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fVis less than fRor if the phase of fVis
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV= fRand both are in phase, then both
φV and φR remain high except for a small minimum time peri-
od when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 9)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC level
will be low at the beginning of a count cycle and will remain
low until the ÷ A counter has counted down from its pro-
grammed value. At this time, MC goes high and remains high
until the ÷ N counter has counted the rest of the way down
from its programmed value (N – A additional counts since
both ÷ N and ÷ A are counting down during the first portion of
the cycle). MC is then set back low, the counters preset to
Reference Address Code Total
Divide
RA2 RA1 RA0
Di
v
id
e
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
128
256
512
1024
1160
2048
www.lansdale.comPage 7 of 35 Issue A
their respective programmed values, and the above sequence
repeated. This provides for a total programmable divide value
(NT)=N•P+A where P and P + 1 represent the dual–modulus
prescaler divide values respectively for high and low MC lev-
els, N the number programmed into the ÷ N counter, and A the
number programmed into the ÷ A counter.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (fR, fVof same
phase and frequency). Pulses low when loop is out of lock.
POWER SUPPLY
VDD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range from
+ 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually-
ground.
LANSDALE Semiconductor, Inc.
ML145152
TYPICAL APPLICATIONS
Figure 1. Synthesizer for Land Mobile Radio VHF Bands
NOTES:
1. Off–chip oscillator optional.
2. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter
Design page for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful
not to exceed the common mode input range of the op amp used in the combiner/loop filter.
LOCK DETECT SIGNAL
10.24 MHz
NOTE 1
R1
MC33171
NOTE 2
+
150 – 175 MHz
5 kHz STEPS
ML12017
÷
64/65 PRESCALER
ML145152
MC
LD
A0A5N9
OSCin
VDD
VSS
OSCoutRA2 RA1
φ
R
φ
V
fin
–
VCO
RA0
N0
+ V
R1
R2 C
R2
C
“1” “1” “1”
NO CONNECTS
CHANNEL PROGRAMMING
www.lansdale.comPage 8of 35 Issue A
LANSDALE Semiconductor, Inc.
ML145152
Figure 2. 666–Channel, Computer–Controlled, Mobile Radiotelephone Synthesizer
for 800 MHz Cellular Radio Systems
LOCK DETECT SIGNAL
R1
+
RECEIVER FIRST L.O.
825.030
→
844.980 MHz
(30 kHz STEPS)
ML12017
÷
64/65 PRESCALER
NOTE 6
ML145152
NOTE 5 MC
LD
A0A5N9
OSCin
VDD
VSS
OSCoutRA2 RA1
φ
R
φ
V
fin
–
VCO
RA0
N0
+ V
R1
R2 C
R2
C
“1” “1” “1”
NO CONNECTS
CHANNEL PROGRAMMING
NOTES:
1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.
2. Duplex operation with 45 MHz receiver/transmit separation.
3.f
R = 7.5 kHz; ÷ R = 2048.
4. Ntotal = N 64 + A = 27501 to 28166; N = 429 to 440; A = 0 to 63.
5. ML145158 may be used where serial data entry is desired.
6. High frequency prescalers may be used for higher frequency VCO and fref
implementations.
7. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page for
additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode
input range of the op amp used in the combiner/loop filter.
REF. OSC.
15.360 MHz
(ON–CHIP OSC.
OPTIONAL) X2
X4
NOTE 6
X4
NOTE 6
TRANSMITTER
MODULATION
TRANSMITTER SIGNAL
825.030
→
844.980 MHz
(30 kHz STEPS)
RECEIVER 2ND L.O.
30.720 MHz
NOTE 7
ML145152 Data Sheet Continued on Page 23
www.lansdale.comPage 9 of 35 Issue A
ML145155
Serial–Input PLL
Frequency Synthesizer
Interfaces with Single–Modulus Prescalers
Legacy Device: Motorola/Freescale MC145155-2
The ML145155 is programmed by a clocked, serial input,
16–bit data stream. The device features consist of a reference
oscillator, selectable–reference divider, digital–phase detector,
14–bit programmable divide–by–N counter, and the necessary
shift register and latch circuitry for accepting serial input
data.
• Operating Temperature Range: TA= – 40 to 85°C
• Low Power Consumption Through Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation with
Buffered Output
• Compatible with the Serial Peripheral Interface (SPI) on
CMOS MCUs
• Lock Detect Signal
• Two Open–Drain Switch Outputs
• 8 User–Selectable ÷ R Values: 16, 512, 1024, 2048,
3668, 4096, 6144, 8192
• Single Modulus/Serial Programming
• ÷ N Range = 3 to 16383
• “Linearized” Digital Phase Detector Enhances Transfer
Function Linearity
• Two Error Signal Options: Single–Ended (Three–State)
or Double–Ended
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates
P DIP 18 = VP
PLASTIC DIP
CASE 707
SOG 20W = -6P
SOG PACKAGE
CASE 751D
1
18
20
1
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
P DIP 18MC145155P2 ML145155VP
SOG 20W MC145155DW2 ML145155-6P
LANSDALE
PACKAGE
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENTS
VDD
φ
V
RA2
RA1
fin
LD
VSS
PDout
φ
RREFout
OSCout
OSCin
RA0
CLK
DATA
ENB
SW1
SW2
14
15
16
17
18
10
11
12
13
5
4
3
2
1
9
8
7
6
PLASTIC DIP
PDout
φ
R
φ
V
RA2
RA1
fin
LD
NC
VSS
VDD 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
NC
REFout
OSCout
OSCin
RA0
CLK
DATA
ENB
SW1
SW2
SOG PACKAGE
NC = NO CONNECTION
www.lansdale.comPage 10 of 35 Issue A
LANSDALE Semiconductor, Inc.
ML145155
14 x 8 ROM REFERENCE DECODER
14–BIT
÷
R COUNTER
φ
V
φ
R
14–BIT
÷
R COUNTER
LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT LD
PDout
fin
VDD
OSCin
OSCout
ENB
14
14
SW2
SW1
fR
fV
LATCH
14–BIT SHIFT REGISTER
DATA 2–BIT SHIFT
REGISTER
CLK
14
REFout
ML145155 BLOCK DIAGRAM
RA2
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (PDIP – Pin 9, SOG – Pin 10)
Input to the ÷ N portion of the synthesizer. fin is typically
derived from loop VCO and is AC coupled into the device. For
larger amplitude signals (standard CMOS logic levels) DC
coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (PDIP – Pins 18, 1, 2; SOG –
Pins 20, 1, 2)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as defined
by the table below:
CLK, DATA
Shift Register Clock, Serial Data Inputs
(PDIP – Pins 10, 11; SOG – Pins 11, 12)
Each low–to–high transition clocks one bit into the on–chip
16–bit shift register. The Data input provides programming
information for the 14–bit ÷ N counter and the two switch
signals SW1 and SW2. The entry format is as follows:
ENB
Latch Enable Input (PDIP – Pin 12, SOG – Pin 13)
When high (1), ENB transfers the contents of the shift reg-
ister into the latches, and to the programmable counter inputs,
and the switch outputs SW1 and SW2. When low (0), ENB
inhibits the above action and thus allows changes to be made
in the shift register data without affecting the counter program-
ming and switch outputs. An on–chip pull–up establishes a
continuously high level for ENB when no external signal is
applied. ENB is normally low and is pulsed high to transfer
data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (PDIP – Pins 17, 16;
SOG – Pins 19, 18)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally–generated refer-
ence signal. This signal is typically ac coupled to OSCin, but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
Reference Address Code Total
Divide
RA2 RA1 RA0
Di
v
id
e
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
512
1024
2048
3668
4096
6144
8192
SW2
SW1
÷
N MSB
÷
N LSB
÷
N COUNTER BITS
LAST DATA BIT IN (BIT NO. 16)
FIRST DATA BIT IN (BIT NO. 1)
www.lansdale.comPage 11 of 35 Issue A
LANSDALE Semiconductor, Inc.
ML145155
ML145155
TYPICAL APPLICATIONS
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface
fin
3
LED DISPLAY
MC14489
KEYBOARD
CMOS
MPU/MCU
ENBCLKDATA
1/2 MC1458*
ML145155
MC120xx
PRESCALER
UHF/VHF
TUNER OR
CATV
FRONT END
4.0 MHz
φ
V
φ
R
+
–
* The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
OUTPUT PINS
PDout
Phase Detector A Output (PDIP, SOG – Pin 6)
Three–state output of phase detector for use as loop error
signal. Double–ended outputs are also available for this pur-
pose (see φV and φR).
Frequency fV> fRor fVLeading: Negative Pulses
Frequency fV< fRor fVLagging: Positive Pulses
Frequency fV= fRand Phase Coincidence: High–Imped-
ance State
φR, φV
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)
These phase detector outputs can be combined externally for
a loop–error signal. A single–ended output is also available for
this purpose (see PDout).
If frequency fVis greater than fRor if the phase of fVis
leading, then error information is provided by fVpulsing low.
fRremains essentially high.
If the frequency fVis less than fRor if the phase of fVis
lagging, then error information is provided by fRpulsing low.
fVremains essentially high.
If the frequency of fV= fRand both are in phase, then both
fVand fRremain high except for a small minimum time peri-
od when both pulse low in phase.
LD
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)
Essentially a high level when loop is locked (fR, fVof same
phase and frequency). LD pulses low when loop is out of lock.
SW1, SW2
Band Switch Outputs (PDIP – Pins 13, 14; SOG – Pins 14, 15)
SW1 and SW2 provide latched open–drain outputs corre-
sponding to data bits numbers one and two. These outputs can
be tied through external resistors to voltages as high as 15 V,
independent of the VDD supply voltage. These are typically
used for band switch functions. A logic 1 causes the output to
assume a high–impedance state, while a logic 0 causes the out-
put to be low.
REFout
Buffered Reference Oscillator Output (PDIP, SOG – Pin 15)
Buffered output of on–chip reference oscillator or externally
provided reference–input signal.
POWER SUPPLY
VDD
Positive Power Supply (PDIP, SOG – Pin 5)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (PDIP, SOG – Pin 7)
The most negative supply potential. This pin is usually
ground.
www.lansdale.comPage 12 of 35 Issue A
Figure 2. AM/FM Radio Synthesizer
TO
AM/FM
OSCILLATORS
TO DISPLAY
ML12019
÷20
PRESCALER
AM
OSC
FM
OSC
fin
KEYBOARD CMOS
MPU/MCU
ENBCLKDATA
1/2 MC1458*
ML145155
2.56 MHz
φ
V
φ
R
+
–
* The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
ML145155
LANSDALE Semiconductor, Inc.
ML145155
www.lansdale.comPage 13 of 35 Issue A
ML145156
Serial–Input PLL
Frequency Synthesizer
Interfaces with Dual–Modulus Prescalers
Legacy Device: Motorola/Freescale MC145156-2
The ML145156 is programmed by a clocked, serial input,
19–bit data stream. The device features consist of a reference
oscillator, selectable–reference divider, digital–phase detector,
10–bit programmable divide–by–N counter, 7–bit program-
mable divide–by–A counter, and the necessary shift register
and latch circuitry for accepting serial input data.
• Operating Temperature Range: TA= – 40 to 85°C
• Low Power Consumption Through Use of
CMOS Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation with
Buffered Output
• Compatible with the Serial Peripheral Interface (SPI) on
CMOS MCUs
• Lock Detect Signal
• Two Open–Drain Switch Outputs
• Dual Modulus/Serial Programming
• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 640,
1000, 1024, 2048
• ÷ N Range = 3 to 1023, ÷A Range = 0 to 127
• “Linearized” Digital Phase Detector Enhances Transfer
Function Linearity
• Two Error Signal Options: Single–Ended (Three–State)
or Double–Ended
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates
1
20
1
20
P DIP 20 = RP
PLASTIC DIP
CASE 738
SOG 20W = -6P
SOG PACKAGE
CASE 751D
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
P DIP 20 MC145156P2 ML145156RP
SOG 20W MC145156DW2 ML145156-6P
LANSDALE
PACKAGE
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
PDout
φ
R
φ
V
RA2
RA1
fin
LD
MC
VSS
VDD 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
TEST
REFout
OSCout
OSCin
RA0
CLK
DATA
ENB
SW1
SW2
www.lansdale.comPage 14 of 35 Issue A
LANSDALE Semiconductor, Inc.
ML145156
12 x 8 ROM REFERENCE DECODER
φ
V
φ
R
12–BIT
÷
R COUNTER
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT LD
PDout
fin
VDD
OSCin
OSCout
ENB
12
10 SW2
SW1
fR
fV
LATCH
DATA 2–BIT SHIFT
REGISTER
CLK
10
REFout
10–BIT SHIFT REGISTER7–BIT SHIFT REGISTER
÷
A COUNTER LATCH
÷
N COUNTER LATCH
7–BIT
÷
A COUNTER 10–BIT
÷
N COUNTER
CONTROL LOGIC
MC
7
7
ML145156 BLOCK DIAGRAM
RA2
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 10)
Input to the positive edge triggered ÷ N and ÷ A counters.
fin is typically derived from a dual–modulus prescaler and is
AC coupled into the device. For larger amplitude signals (stan-
dard CMOS logic levels), DC coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 20, 1, 2)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as defined
by the table below:
CLK, DATA
Shift Register Clock, Serial Data Inputs (Pins 11, 12)
Each low–to–high transition clocks one bit into the on–chip
19–bit shift register. The data input provides programming in-
formation for the 10–bit ÷ N counter, the 7–bit ÷ A counter,
and the two switch signals SW1 and SW2. The entry format is
as follows:
ENB
Latch Enable Input (Pin 13)
When high (1), ENB transfers the contents of the shift reg-
ister into the latches, and to the programmable counter inputs,
and the switch outputs SW1 and SW2. When low (0), ENB
inhibits the above action and thus allows changes to be made
in the shift register data without affecting the counter program-
ming and switch outputs. An on–chip pull–up establishes a
continuously high level for ENB when no external signal is
applied. ENB is normally low and is pulsed high to transfer
data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 19, 18)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally–generated refer-
ence signal. This signal is typically AC coupled to OSCin, but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
TEST
Factory Test Input (Pin 16)
Used in manufacturing. Must be left open or tied to VSS.
Reference Address Code Total
Divide
RA2 RA1 RA0
Di
v
id
e
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
128
256
640
1000
1024
2048
SW2
SW1
÷
N MSB
A LSB
÷
N COUNTER BITS
LAST DATA BIT IN (BIT NO. 19)
FIRST DATA BIT IN (BIT NO. 1)
A COUNTER BITS
N LSB
÷
÷
A MSB
www.lansdale.comPage 15 of 35 Issue A
ML145156
OUTPUT PINS
PDout
Phase Detector A Output (Pin 6)
Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this pur-
pose (see φVand φR).
Frequency fV> fRor fVLeading: Negative Pulses
Frequency fV< fRor fVLagging: Positive Pulses
Frequency fV= fRand Phase Coincidence: High–Imped-
ance State
φR, φV
Phase Detector B Outputs (Pins 4, 3)
These phase detector outputs can be combined externally for
a loop–error signal. A single–ended output is also available for
this purpose (see PDout).
If frequency fVis greater than fRor if the phase of fVis
leading, then error information is provided by φVpulsing low.
φRremains essentially high.
If the frequency fVis less than fRor if the phase of fVis
lagging, then error information is provided by φRpulsing low.
φVremains essentially high.
If the frequency of fV= fRand both are in phase, then both
φVand φRremain high except for a small minimum time
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 8)
Signal generated by the on–chip control logic circuitry for-
controlling an external dual–modulus prescaler. The MC level-
will be low at the beginning of a count cycle and will remain-
low until the ÷ A counter has counted down from its pro-
grammed value. At this time, MC goes high and remains high-
until the ÷ N counter has counted the rest of the way down-
from its programmed value (N – A additional counts since
both ÷ N and ÷ A are counting down during the first portion of
the cycle). MC is then set back low, the counters preset to their
respective programmed values, and the above sequence repeat-
ed. This provides for a total programmable divide value (NT) =
N • P + A where P and P + 1 represent the dual–modulus
prescaler divide values respectively for high and low MC lev-
els, N the number programmed into the ÷ N counter, and A the
number programmed into the ÷ A counter.
LD
Lock Detector Output (Pin 9)
Essentially a high level when loop is locked (fR, fVof same
phase and frequency). LD pulses low when loop is out of lock.
SW1, SW2
Band Switch Outputs (Pins 14, 15)
SW1 and SW2 provide latched open–drain outputs corre-
sponding to data bits numbers one and two. These outputs can
be tied through external resistors to voltages as high as 15 V,
independent of the VDD supply voltage. These are typically
used for band switch functions. A logic 1 causes the output to
assume a high–impedance state, while a logic 0 causes the out-
put to be low.
REFout
Buffered Reference Oscillator Output (Pin 17)
Buffered output of on–chip reference oscillator or externally
provided reference–input signal.
POWER SUPPLY
VDD
Positive Power Supply (Pin 5)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (Pin 7)
The most negative supply potential. This pin is usually-
ground.
LANSDALE Semiconductor, Inc.
ML145156
www.lansdale.comPage 16 of 35 Issue A
TYPICAL APPLICATIONS
Figure 1. AM/FM Radio Broadcast Synthesizer
SW2SW1
φ
V
φ
R
PDout
MC
finENBDATACLK
REFout
VSS
VDD
LDRA0RA1RA2OSCin OSCout
NOTES 1
AND 2
OPTIONAL
LOOP
ERROR SIGNAL
ML12019
÷
20/21 DUAL MODULUS PRESCALER
VCO
AM B +
+ 12 V FM B +
+ 12 V
LOCK DETECT SIGNAL
TO DISPLAY DRIVER (e.g., MC14489)
CMOS MPU/MCU
KEY–
BOARD
+ V
3.2 MHz
ML145156
1/2 MC1458
NOTE 3
+
–
NOTES:
1. For AM: channel spacing = 5 kHz,
÷
R =
÷
640 (code 100).
2. For FM: channel spacing = 25 kHz,
÷
R =
÷
128 (code 010).
3. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the
common mode input range of the op amp used in the combiner/loop filter.
Figure 2. Avionics Navigation or Communication Synthesizer
NAV = 01
COM = 10
CHANNEL
SELECTION
VCO
LOCK DETECT SIGNAL
TO DISPLAY DRIVER
(e.g., MC14489)
CMOS MPU/MCU
+ V
3.2 MHz (NOTE 3)
ML145156
MC33171
NOTE 5
SW2SW1
φ
V
φ
R
PDout
MC
finENBDATACLK
REFout
VSS
VDD
LDRA0RA1RA2OSCin OSCout
ML12016 (NOTES 2 AND 4)
÷
40/41 DUAL MODULUS PRESCALER
+
–
VCO RANGE
NAV: 97.300 – 107.250 MHz
COM–T: 118.000 – 135.975 MHz
COM–R: 139.400 – 157.375 MHz
R/T
NOTES:
1. For NAV: fR = 50 kHz,
÷
R = 64 using 10.7 MHz lowside injection, Ntotal = 1946 – 2145.
For COM–T: fR = 25 kHz,
÷
R = 128, Ntotal = 4720 – 5439.
For COM–R: fR = 25 kHz,
÷
R = 128, using 21.4 MHz highside injection, Ntotal = 5576 – 6295.
2. A
÷
32/33 dual modulus approach is provided by substituting an ML12015 for the ML12016. The devices are pin equivalent.
3. A 6.4 MHz oscillator crystal can be used by selecting
÷
R = 128 (code 010) for NAV and
÷
R = 256 (code 011) for COM.
4. ML12013 + MC10131 combination may also be used to form the
÷
40/41 prescaler.
5. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design
page for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed
the common mode input range of the op amp used in the combiner/loop filter.
ML145156 Data Sheet Continued on Page 23
LANSDALE Semiconductor, Inc.
ML145156
ML145156
www.lansdale.comPage 17 of 35 Issue A
ML145157
Serial–Input PLL
Frequency Synthesizer
Interfaces with Single–Modulus Prescalers
Legacy Device: Motorola/Freescale MC145157-2
The ML145157 has a fully programmable 14–bit reference
counter, as well as a fully programmable ÷ N counter. The
counters are programmed serially through a common data
input and latched into the appropriate counter latch, accord-
ing to the last data bit (control bit) entered.
• Operating Temperature Range: TA= – 40 to 85°C
• Low Power Consumption Through Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• Fully Programmable Reference and ÷ N Counters
• ÷ R Range = 3 to 16383
• ÷ N Range = 3 to 16383
• fVand fROutputs
• Lock Detect Signal
• Compatible with the Serial Peripheral Interface
(SPI) on CMOS MCUs
• “Linearized” Digital Phase Detector
• Single–Ended (Three–State) or Double–Ended Phase
Detector Outputs
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates
P DIP 16 = EP
PLASTIC DIP
CASE 648
SOG 16 = -5P
SOG PACKAGE
CASE 751G
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
P DIP 16 MC145157P2 ML145157EP
SOG 20W MC145157DW2 ML145157-5P
LANSDALE
PACKAGE
1
16
1
16
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
S/Rout
fR
REFout
φ
V
φ
R
CLK
DATA
ENB
VDD
fV
OSCout
OSCin
fin
LD
VSS
PDout
www.lansdale.comPage 18of 35 Issue A
LANSDALE Semiconductor, Inc.
ML145157
14–BIT SHIFT REGISTER
14–BIT ÷
N COUNTER
φ
V
ML145157 BLOCK DIAGRAM
φ
R
REFERENCE COUNTER LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT LD
PDout
fin
OSCin
OSCout
ENB
14
14
14–BIT SHIFT REGISTER
DATA
CLK
14
REFout
÷
N COUNTER LATCH
14–BIT ÷
R COUNTER
14
S/Rout
fR
fV
1–BIT
CONTROL
S/R
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on
this input decrements the ÷ N counter. This input has an invert-
er biased in the linear region to allow use with AC coupled sig-
nals as low as 500 mV p–p. For larger amplitude signals (stan-
dard CMOS logic levels), DC coupling may be used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low–to–high transition of the clock shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic
1selects the reference counter latch and a logic 0 selects the
÷ N counter latch. The entry format is as follows:
ENB
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift regis-
ter into the reference divider or ÷ N latches depending on the
control bit. The reference divider latches are activated if the
control bit is at a logic high and the ÷ N latches are activated if
the control bit is at a logic low. A logic low on this pin allows
the user to change the data in the shift registers without affect-
ing the counters. ENB is normally low and is pulsed high to
transfer data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally–generated refer-
ence signal. This signal is typically AC coupled to OSCin, but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
OUTPUT PINS
PDout
Single–Ended Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output pro-
duces a loop–error signal that is used with a loop filter to con-
trol a VCO.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence:
High–Impedance State
φR, φV
Double–Ended Phase Detector B Outputs (Pins 16, 15)
These outputs can be combined externally for a loop–error
signal. A single–ended output is also available for this purpose
(see PDout).
LSB
MSB
CONTROL
FIRST DATA BIT INTO SHIFT REGISTER
www.lansdale.comPage 19 of 35 Issue A
ML145157
If frequency fVis greater than fRor if the phase of fVis
leading, then error information is provided by φVpulsing low.
φRremains essentially high.
If the frequency fVis less than fRor if the phase of fV is
lagging, then error information is provided by φRpulsing low.
φVremains essentially high.
If the frequency of fV= fRand both are in phase, then both
φVand φRremain high except for a small minimum time peri-
od when both pulse low in phase.
fR,f
V
RCounter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and fin frequency outputs. The
fRand fVoutputs are connected internally to the ÷ R and ÷ N
counter outputs respectively, allowing the counters to be used
independently, as well as monitoring the phase detector inputs.
LD
Lock Detector Output (Pin 7)
This output is essentially at a high level when the loop is
locked (fR, fVof same phase and frequency), and pulses low
when loop is out of lock.
REFout
Buffered Reference Oscillator Output (Pin 14)
This output can be used as a second local oscillator, refer-
ence oscillator to another frequency synthesizer, or as the sys-
tem clock to a microprocessor controller.
S/Rout
Shift Register Output (Pin 12)
This output can be connected to an external shift register to
provide band switching, control information, and counter pro-
gramming code checking.
POWER SUPPLY
VDD
Positive Power Supply (Pin 4)
The positive power supply potential. This pin may range
from +3 to +9 V with respect to VSS.
VSS
Negative Power Supply (Pin 6)
The most negative supply potential. This pin is usually
ground.
LANSDALE Semiconductor, Inc.
ML145157
www.lansdale.comPage 20 of 35 Issue A
ML145158
Serial–Input PLL
Frequency Synthesizer
Interfaces with Dual–Modulus Prescalers
Legacy Device: Motorola/Freescale MC145158-2
The ML145158 has a fully programmable 14–bit reference
counter, as well as fully programmable ÷ N and ÷ A counters.
The counters are programmed serially through a common
data input and latched into the appropriate counter latch,
according to the last data bit (control bit) entered.
• Operating Temperature Range: TA = – 40 to 85°C
• Low Power Consumption Through Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• Fully Programmable Reference and ÷ N Counters
• ÷ R Range = 3 to 16383
• ÷ N Range = 3 to 1023
• Dual Modulus Capability; ÷ A Range = 0 to 127
• fVand fROutputs
• Lock Detect Signal
• Compatible with the Serial Peripheral Interface (SPI) on
CMOS MCUs
• “Linearized” Digital Phase Detector
• Single–Ended (Three–State) or Double–Ended Phase
Detector Outputs
• Chip Complexity: 6504 FETs or 1626
Equivalent Gates
1
16
1
16
P DIP 16 = EP
PLASTIC DIP
CASE 648
SOG 16 = -5P
SOG PACKAGE
CASE 751G
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
P DIP 16 MC145158P2 ML145158EP
SOG 16 MC145158DW2 ML145158-5P
LANSDALE
PACKAGE
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
MC
fR
REFout
φ
V
φ
R
CLK
DATA
ENB
VDD
fV
OSCout
OSCin
fin
LD
VSS
PDout
www.lansdale.comPage 21 of 35 Issue A
ML145158
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
INPUT PINS
fin Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on
this input decrements the ÷ A and ÷ N counters. This input has
an inverter biased in the linear region to allow use with AC
coupled signals as low as 500 mV p–p. For larger amplitude
signals (standard CMOS logic levels), DC coupling may be
used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low–to–high transition of the CLK shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
÷ A, ÷ N counter latch. The data entry format is as follows:
ENB
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift regis-
ter into the reference divider or ÷ N, ÷ A latches depending on
the control bit. The reference divider latches are activated if the
control bit is at a logic high and the ÷ N, ÷ A latches are acti-
vated if the control bit is at a logic low. A logic low on this pin
allows the user to change the data in the shift registers without
affecting the counters. ENB is normally low and is pulsed high
to transfer data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally–generated refer-
ence signal. This signal is typically AC coupled to OSCin, but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
LSB
MSB
CONTROL
FIRST DATA BIT INTO SHIFT REGISTER
÷
R
MSB
CONTROL
÷
N
FIRST DATA BIT INTO SHIFT REGISTER
÷
A
LSB
MSB
LSB
14–BIT SHIFT REGISTER
7–BIT
÷
A
COUNTER
φ
V
ML145158 BLOCK DIAGRAM
φ
R
REFERENCE COUNTER LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT LD
PDout
fin
OSCin
OSCout
ENB
14
10
7–BIT S/R
DATA
CLK
10
REFout
÷
A COUNTER
LATCH
14–BIT
÷
R
COUNTER
14
MC
fR
fV
1–BIT
CONTROL
S/R 10–BIT S/R
÷
N COUNTER
LATCH
10–BIT
÷
N
COUNTER
CONTROL LOGIC
7
7
www.lansdale.comPage 22 of 35 #
ML145158
OUTPUT PINS
PDout
Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output pro-
duces a loop–error signal that is used with a loop filter to con-
trol a VCO.
Frequency fV> fRor fVLeading: Negative Pulses
Frequency fV< fRor fVLagging: Positive Pulses
Frequency fV= fRand Phase Coincidence:
High–Impedance State
φR, φV
Phase Detector B Outputs (Pins 16, 15)
Double–ended phase detector outputs. These outputs can be
combined externally for a loop–error signal. A single–ended
output is also available for this purpose (see PDout).
If frequency fVis greater than fRor if the phase of fVis
leading, then error information is provided by φVpulsing low.
φRremains essentially high.
If the frequency fVis less than fRor if the phase of fVis
lagging, then error information is provided by φRpulsing low.
φVremains essentially high.
If the frequency of fV= fRand both are in phase, then both
φVand φRremain high except for a small minimum time peri-
od when both pulse low in phase.
MC
Dual–Modulus Prescaler Control Output (Pin 12)
This output generates a signal by the on–chip control logic
circuitry for controlling an external dual–modulus prescaler.
The MC level is low at the beginning of a count cycle and
remains low until the ÷ A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both ÷ N and ÷ A are counting down during the first por-
tion of the cycle). MC is then set back low, the counters preset
to their respective programmed values, and the above sequence
repeated. This provides for a total programmable divide value
(NT) = N • P + A where P and P + 1 represent the dual–modu-
lus prescaler divide values respectively for high and low modu-
lus control levels, N the number programmed into the ÷ N
counter, and A the number programmed into the ÷ A counter.
Note that when a prescaler is needed, the dual–modulus ver-
sion offers a distinct advantage. The dual–modulus prescaler
allows a higher reference frequency at the phase detector input,
increasing system performance capability, and simplifying the
loop filter design.
fR,f
V
R Counter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and fin frequency outputs. The
fR and fVoutputs are connected internally to the ÷ R and ÷ N
counter outputs respectively, allowing the counters to be used
independently, as well as monitoring the phase detector inputs.
LD
Lock Detector Output (Pin 7)
This output is essentially at a high level when the loop is
locked (fR, fVof same phase and frequency), and pulses low
when loop is out of lock.
REFout
Buffered Reference Oscillator Output (Pin 14)
This output can be used as a second local oscillator, refer-
ence oscillator to another frequency synthesizer, or as the sys-
tem clock to a microprocessor controller.
POWER SUPPLY
VDD
Positive Power Supply (Pin 4)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (Pin 6)
The most negative supply potential. This pin is usually-
ground.
ML145158
LANSDALE Semiconductor, Inc.
www.lansdale.comPage 23 of 35 Issue A
LANSDALE Semiconductor, Inc.
ML1451xx
ML14515X FAMILY CHARACTERISTICS AND DESCRIPTIONS - CONTINUED
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 10.0 V
Vin, Vout Input or Output Voltage (DC or Transient)
except SW1, SW2
– 0.5 to VDD + 0.5 V
Vout Output Voltage (DC or Transient),
SW1, SW2 (Rpull–up = 4.7 kΩ)
– 0.5 to + 15 V
Iin, Iout Input or Output Current (DC or Transient),
per Pin
±10 mA
IDD, ISS Supply Current, VDD or VSS Pins ±30 mA
PDPower Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 C
TLLead Temperature, 1 mm from Case for
10 seconds
260 C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
†Power Dissipation Temperature Derating:
Plastic DIP: – 12 mW/ C from 65 to 85C
SOG Package: – 7 mW/ C from 65 to 85C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
V
DD
– 40 C 25 C 85C
Symbol Parameter Test Condition
VDD
VMin Max Min Max Min Max Unit
VDD Power Supply Voltage
Range
– 3 9 3 9 3 9 V
Iss Dynamic Supply Current fin = OSCin = 10 MHz,
1 V p–p AC coupled sine
wave
R = 128, A = 32, N = 128
3
5
9
–
–
–
3.5
10
30
–
–
–
3
7.5
24
–
–
–
3
7.5
24
mA
ISS Quiescent Supply Current
(not including pull–up
current component)
Vin = VDD or VSS
Iout = 0 µA
3
5
9
–
–
–
800
1200
1600
–
–
–
800
1200
1600
–
–
–
1600
2400
3200
µA
Vin Input Voltage – fin, OSCin Input AC coupled sine wave – 500 – 500 – 500 – mV p–p
VIL LowLevel Input V oltage
– fin, OSCin
Vout 2.1 V Input DC
Vout 3.5 V coupled
Vout 6.3 V square wave
3
5
9
–
–
–
0
0
0
–
–
–
0
0
0
–
–
–
0
0
0
V
VIH High–Level Input Voltage
– fin, OSCin
Vout 0.9 V Input DC
Vout 1.5 V coupled
Vout 2.7 V square wave
3
5
9
3.0
5.0
9.0
–
–
–
3.0
5.0
9.0
–
–
–
3.0
5.0
9.0
–
–
–
V
VIL Low–Level Input Voltage
– except fin, OSCin
3
5
9
–
–
–
0.9
1.5
2.7
–
–
–
0.9
1.5
2.7
–
–
–
0.9
1.5
2.7
V
VIH High–Level Input Voltage
– except fin, OSCin
3
5
9
2.1
3.5
6.3
–
–
–
2.1
3.5
6.3
–
–
–
2.1
3.5
6.3
–
–
–
V
Iin Input Current (fin, OSCin) Vin = VDD or VSS 9±2±50 ±2±25 ±2±22 µA
IIL Input Leakage Current
(Data, CLK, ENB –
without pull–ups)
Vin = VSS 9 – – 0.3 –– 0.1 –– 1.0 µA
IIH Input Leakage Current (all
inputs except fin, OSCin)
Vin = VDD 9 – 0.3 – 0.1 – 1.0 µA
(continued)
These devices contain protection circuitry to
protect against damage due to high static
voltages or electric fields. However, precau-
tions must be taken to avoid applications of any
voltage higher than maximum rated voltages
to these high–impedance circuits. For proper
operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD
except for SW1 and SW2.
SW1 and SW2 can be tied through external
resistors to voltages as high as 15 V, indepen-
dent of the supply voltage.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD), except for inputs with pull–up devices.
Unused outputs must be left open.
www.lansdale.comPage 24 of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
DC ELECTRICAL CHARACTERISTICS (continued)
V
DD
– 40 C 25 C 85C
Symbol Parameter Test Condition
VDD
VMin Max Min Max Min Max Unit
IIL Pull–up Current (all inputs
with pull–ups)
Vin = VSS 9– 20 – 400 – 20 – 200 – 20 – 170 µA
Cin Input Capacitance – – 10 – 10 – 10 pF
VOL Low–Level Output
Voltage – OSCout
Iout 0 µA
Vin = VDD
3
5
9
–
–
–
0.9
1.5
2.7
–
–
–
0.9
1.5
2.7
–
–
–
0.9
1.5
2.7
V
VOH High–Level Output
Voltage – OSCout
Iout 0 µA
Vin = VSS
3
5
9
2.1
3.5
6.3
–
–
–
2.1
3.5
6.3
–
–
–
2.1
3.5
6.3
–
–
–
V
VOL Low–Level Output
Voltage – Other Outputs
Iout 0 µA 3
5
9
–
–
–
0.05
0.05
0.05
–
–
–
0.05
0.05
0.05
–
–
–
0.05
0.05
0.05
V
VOH High–Level Output
Voltage – Other Outputs
Iout 0 µA 3
5
9
2.95
4.95
8.95
–
–
–
2.95
4.95
8.95
–
–
–
2.95
4.95
8.95
–
–
–
V
V(BR)DSS Drain–to–Source
Breakdown Voltage –
SW1, SW2
Rpull–up = 4.7 kΩ– 15 – 15 – 15 – V
IOL Low–Level Sinking
Current – MC
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
1.30
1.90
3.80
–
–
–
1.10
1.70
3.30
–
–
–
0.66
1.08
2.10
–
–
–
mA
IOH High–Level Sourcing
Current – MC
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
– 0.60
– 0.90
– 1.50
–
–
–
– 0.50
– 0.75
– 1.25
–
–
–
– 0.30
– 0.50
– 0.80
–
–
–
mA
IOL Low–Level Sinking
Current – LD
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.25
0.64
1.30
–
–
–
0.20
0.51
1.00
–
–
–
0.15
0.36
0.70
–
–
–
mA
IOH High–Level Sourcing
Current – LD
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
– 0.25
– 0.64
– 1.30
–
–
–
– 0.20
– 0.51
– 1.00
–
–
–
– 0.15
– 0.36
– 0.70
–
–
–
mA
IOL Low–Level Sinking
Current – SW1, SW2
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.80
1.50
3.50
–
–
–
0.48
0.90
2.10
–
–
–
0.24
0.45
1.05
–
–
–
mA
IOL Low–Level Sinking
Current – Other Outputs
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.44
0.64
1.30
–
–
–
0.35
0.51
1.00
–
–
–
0.22
0.36
0.70
–
–
–
mA
IOH High–Level Sourcing
Current – Other Outputs
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
– 0.44
– 0.64
– 1.30
–
–
–
– 0.35
– 0.51
– 1.00
–
–
–
– 0.22
– 0.36
– 0.70
–
–
–
mA
IOZ Output Leakage Current –
PDout
Vout = VDD or VSS
Output in Off State
9 – ±0.3 – ±0.1 – ±1.0 µA
IOZ Output Leakage Current –
SW1, SW2
Vout = VDD or VSS
Output in Off State
9 – ±0.3 – ±0.1 – ±3.0 µA
Cout Output Capacitance –
PDout
PDout – Three–State – – 10 – 10 – 10 pF
www.lansdale.comPage 25 of 35 Issue A
LANSDALE Semiconductor, Inc.
ML1451xx
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 10 ns)
Symbol Parameter
VDD
V
Guaranteed Limit
255C
Guaranteed Limit
– 40 to 85°CUnit
tPLH, tPHL Maximum Propagation Delay, fin to MC
(Figures 1 and 4)
3
5
9
110
60
35
120
70
40
ns
tPHL Maximum Propagation Delay, ENB to SW1, SW2
(Figures 1 and 5)
3
5
9
160
80
50
180
95
60
ns
twOutput Pulse Width, φR, φV, and LD with fR in Phase with fV
(Figures 2 and 4)
3
5
9
25 to 200
20 to 100
10 to 70
25 to 260
20 to 125
10 to 80
ns
tTLH Maximum Output Transition Time, MC
(Figures 3 and 4)
3
5
9
115
60
40
115
75
60
ns
tTHL Maximum Output Transition Time, MC
(Figures 3 and 4)
3
5
9
60
34
30
70
45
38
ns
tTLH, tTHL Maximum Output Transition Time, LD
(Figures 3 and 4)
3
5
9
180
90
70
200
120
90
ns
tTLH, tTHL Maximum Output Transition Time, Other Outputs
(Figures 3 and 4)
3
5
9
160
80
60
175
100
65
ns
SWITCHING WAVEFORMS
TEST POINT
DEVICE
UNDER
TEST CL*
* Includes all probe and fixture capacitance.
TEST POINT
DEVICE
UNDER
TEST CL*
* Includes all probe and fixture capacitance.
VDD
15 k
Ω
tTLH
90%
10%
tTHL
ANY
OUTPUT
Figure 1. Figure 2.
50%
OUTPUT
50%
INPUT
tPLH
– V SS
VDD
tPHL 50%
φ
R,
φ
V, LD*
*f
R in phase with fV.
tw
OUTPUTOUTPUT
Figure 3.
Figure 4. Test Circuit Figure 5. Test Circuit
www.lansdale.comPage 26 of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
TIMING REQUIREMENTS (Input tr = tf = 10 ns unless otherwise indicated)
Symbol Parameter
VDD
V
Guaranteed Limit
25 C
Guaranteed Limit
– 40 to 85C Unit
fclk Serial Data Clock Frequency, Assuming 25% Duty Cycle
NOTE: Refer to CLK tw(H) below
(Figure 6)
3
5
9
DC to 5.0
DC to 7.1
DC to 10
DC to 3.5
DC to 7.1
DC to 10
MHz
tsu Minimum Setup Time, Data to CLK
(Figure 7)
3
5
9
30
20
18
30
20
18
ns
thMinimum Hold Time, CLK to Data
(Figure 7)
3
5
9
40
20
15
40
20
15
ns
tsu Minimum Setup Time, CLK to ENB
(Figure 7)
3
5
9
70
32
25
70
32
25
ns
trec Minimum Recovery Time, ENB to CLK
(Figure 7)
3
5
9
5
10
20
5
10
20
ns
tw(H) Minimum Pulse Width, CLK and ENB
(Figure 6)
3
5
9
50
35
25
70
35
25
ns
tr, tfMaximum Input Rise and Fall Times – Any Input
(Figure 8)
3
5
9
5
4
2
5
4
2
µs
SWITCHING WAVEFORMS
Figure 6.
Figure 7.
VSS
– VDD
50%
50%
LAST
CLK
PREVIOUS
DATA
LATCHED
FIRST
CLK
ENB
CLK
DATA 50%
– VDD
VSS
– VDD
VSS
– VDD
VSS
tsu
tsu trec
th
50%
CLK,
ENB
tw(H)
– VDD
VSS
4 fclk
1*
*Assumes 25% Duty Cycle.
tr
90%
10%
tf
ANY
OUTPUT
Figure 8.
www.lansdale.comPage 27 of 35 Issue A
LANSDALE Semiconductor, Inc.
ML1451xx
FREQUENCY CHARACTERISTICS (Voltages References to VSS, CL = 50 pF, Input tr = tf =10 ns unless otherwise indicated)
V
DD
– 40 C 25 C 85C
Symbol Parameter Test Condition
VDD
VMin Max Min Max Min Max Unit
fiInput Frequency
(fin, OSCin)
R ≥ 8, A ≥ 0, N ≥ 8
Vin = 500 mV p–p
AC coupled sine wave
3
5
9
–
–
–
6
15
15
–
–
–
6
15
15
–
–
–
6
15
15
MHz
R ≥ 8, A ≥ 0, N ≥ 8
Vin = 1 V p–p AC coupled
sine wave
3
5
9
–
–
–
12
22
25
–
–
–
12
20
22
–
–
–
7
20
22
MHz
R ≥ 8, A ≥ 0, N ≥ 8
Vin = VDD to VSS
DC coupled square wave
3
5
9
–
–
–
13
25
25
–
–
–
12
22
25
–
–
–
8
22
25
MHz
NOTE: Usually, the PLL's propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency limit of the system.
The upper frequency limit is found with the following formula: f = P /(tP + tset) where f is the upper frequency in Hz, P is the lower of the dual
modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and tset is the prescaler setup time in seconds.
For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A prescaler is used, the setup time is 16 ns. Thus, if the 64/65
ratio is utilized, the upper frequency limit is f = P / (tP + tset) = 64/(70 + 16) = 744 MHz.
VH= High Voltage Level.
VL= Low Voltage Level.
* At this point, when both fR and fV are in phase, the output is forced to near mid–supply.
NOTE: The PDout generates error pulses during out–of–lock conditions. When locked in phase and frequency the output is high
and the voltage at this pin is determined by the low–pass filter capacitor.
fR
REFERENCE
OSC
÷
R
fV
FEEDBACK
(fin
÷
N)
PDout
φ
R
φ
V
LD
*
VH
VL
VH
VL
VH
HIGH IMPEDANCE
VH
VL
VH
VL
VH
VL
VL
Figure 9. Phase Detector/Lock Detector Output Waveforms
www.lansdale.comPage 28of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
DESIGN CONSIDERATIONS
PHASE–LOCKED LOOP – LOW–PASS FILTER DESIGN
C)
_
+A
C
R2
C
VCO
C
VCO
R2
B)
A)
C
VCO
PDout
PDout
φ
R –
φ
V –
PDout –
φ
R
φ
V
R1
R1
R1
R1
R2
NOTE: Sometimes R1 is split into two series resistors, each R1 ÷2. A capacitor CC is then placed from the midpoint to ground to further
filter φV and φR. The value of CC should be such that the corner frequency of this network does not significantly affect ωn.
The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
DEFINITIONS:
N = Total Division Ratio in feedback loop
Kφ (Phase Detector Gain) = VDD/4π for PDout
Kφ (Phase Detector Gain) = VDD/2π for φV and φR
KVCO (VCO Gain) = 2π∆fVCO
∆VVCO
for a typical design wn (Natural Frequency) 2πfr
10 (at phase detector input).
Damping Factor: ζ ≅ 1
RECOMMENDED READING:
Gardner, Floyd M.,
Phaselock Techniques (second edition).
New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim,
Frequency Synthesizers: Theory and Design (second edition).
New York, Wiley–Interscience, 1980.
Blanchard, Alain,
Phase
–
Locked Loops: Application to Coherent Receiver Design.
New York, Wiley–Interscience, 1976.
Egan, William F.,
Frequency Synthesis by Phase Lock.
New York, Wiley–Interscience, 1981.
Rohde, Ulrich L.,
Digital PLL Frequency Synthesizers Theory and Design.
Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M.,
Design of Phase
–
Locked Loop Circuits, with Experiments.
Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold,
The PLL Synthesizer Cookbook.
Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from
Electronic Design,
1987.
φ
R –
φ
V –
F(s) =
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =
ζ
=
ω
n = NR1C
R1sC + 1
ω
n =
ζ
=
ω
nR2C
2
R2sC + 1
R1sC
1
N
ω
n
2K
φ
KVCO
F(s) =
ζ
=
ω
n =
(R
()
1+R
2)sC + 1
R2sC + 1
NC(R1 + R2)
R2C+ N
K
φ
KVCO
K
φ
KVCO
NCR1
0.5
ω
n
K
φ
KVCO
K
φ
KVCO
www.lansdale.comPage 29 of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a refer-
ence frequency to Motorola's or Lansdale’s CMOS frequency
synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
may be direct or DC coupled to OSCin. In general, the highest
frequency capability is obtained utilizing a direct–coupled
square wave having a rail–to–rail (VDD to VSS) voltage
swing. If the oscillator does not have CMOS logic levels on the
outputs, capacitive or AC coupling to OSCin may be used.
OSCout, an unbuffered output, should be left floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog, the Gold Book, or similar
publications.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the ML12061 MECL device. The reference signal from the
MECL device is AC coupled to OSCin. For large amplitude
signals (standard CMOS logic levels), DC coupling is used.
OSCout, an unbuffered output, should be left floating. In gen-
eral, the highest frequency capability is obtained with a di-
rect–coupled square wave having rail–to–rail voltage swing.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an ap-
propriate crystal may be used to provide a reference source fre-
quency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 10.
For VDD = 5.0 V, the crystal should be specified for a loading
capacitance, CL, which does not exceed 32 pF for frequencies to
approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to
15 MHz, and 10 pF for higher frequencies. These are guidelines
that provide a reasonable compromise between IC capacitance,
drive capability, swamping variations in stray and IC input/output
capacitance, and realistic CLvalues. The shunt load capacitance,
CL, presented across the crystal can be estimated to be:
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the OSCin and
OSCout pins to minimize distortion, stray capacitance, stray
inductance, and startup stabilization time. In some cases, stray
capacitance should be added to the value for Cin and Cout.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 12. The drive level specified by the crys-
tal manufacturer is the maximum stress that a crystal can with-
stand without damage or excessive shift in frequency. R1 in
Figure 10 limits the drive level. The use of R1 may not be nec-
essary in some cases (i.e., R1 = 0 Ω).
To verify that the maximum DC supply voltage does not
overdrive the crystal, monitor the output frequency as a func-
tion of voltage at OSCout. (Care should be taken to minimize
loading.) The frequency should increase very slightly as the
DC supply voltage is increased. An overdriven crystal will
decrease in frequency or become unstable with an increase in
supply voltage. The operating supply voltage must be reduced
or R1 must be increased in value if the overdriven condition
exists. The user should note that the oscillator start–up time is
proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed
expertise in CMOS oscillator design with crystals. Discussions
with such manufacturers can prove very helpful (see Table 1).
Figure 10. Pierce Crystal Oscillator Circuit
R1*
C2C1
FREQUENCY
SYNTHESIZER
OSCout
OSCin
* May be deleted in certain cases. See text.
Rf
CL = CinCout
Cin + Cout
+ Ca + Co + C1 •C2
C1 + C2
where
Cin = 5 pF (see Figure 11)
Cout = 6 pF (see Figure 11)
Ca= 1 pF (see Figure 11)
CO= the crystal's holder capacitance
(see Figure 12)
C1 and C2 = external capacitors (see Figure 10)
Figure 11. Parasitic Capacitances of the Amplifier
Cin Cout
Ca
Figure 12. Equivalent Crystal Networks
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
2
1
2
121
RSLSCS
ReXe
CO
www.lansdale.comPage 30 of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2
Feb.,1969.
D. Kemper, L. Rosine, “Quartz Crystals for
FrequencyControl”, Electro–Technology, June, 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
DUAL–MODULUS PRESCALING
OVERVIEW
The technique of dual–modulus prescaling is well estab-
lished as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low–frequency programmable coun-
ters to be used as high–frequency programmable counters with
speed capability of several hundred MHz. This is possible with
out the sacrifice in system resolution and performance that
results if a fixed (single–modulus) divider is used for the
prescaler.
In dual–modulus prescaling, the lower speed counters must
be uniquely configured. Special control logic is necessary to
select the divide value P or P + 1 in the prescaler for the
required amount of time (see modulus control definition).
Lansdale's dual–modulus frequency synthesizers contain this
feature and can be used with a variety of dual–modulus-
prescalers to allow speed, complexity and cost to be tailored to
the system requirements. Prescalers having P, P + 1 divide val-
ues in the range of ÷ 3/÷4 to ÷128/÷ 129 can be controlled by
most Lansdale frequency synthesizers.
Several dual–modulus prescaler approaches suitable for use
with the MC145152 (Motorola), ML145156, or ML145158 are:
DESIGN GUIDELINES
The system total divide value, N total (NT) will be dictated
by the application:
N is the number programmed into the ÷ N counter, A is the
number programmed into the ÷ A counter, P and P + 1 are the
two selectable divide ratios available in the dual–modulus
prescalers. To have a range of NTvalues in sequence, the
÷ A counter is programmed from zero through P – 1 for a par-
ticular value N in the ÷ N counter. N is then incremented to N
+ 1 and the ÷ A is sequenced from 0 through P – 1 again.
There are minimum and maximum values that can be
achieved for NT. These values are a function of P and the size
of the ÷ N and ÷ A counters.
The constraint N ≥A always applies. If Amax = P – 1, then
Nmin ≥P – 1. Then NTmin = (P – 1) P + A or (P – 1) P since
A is free to assume the value of 0.
NTmax = Nmax • P + Amax
To maximize system frequency capability, the dual–modulus
prescaler output must go from low to high after each group of
P or P + 1 input cycles. The prescaler should divide by P when
its modulus control line is high and by P + 1 when its MC is
low.
For the maximum frequency into the prescaler (fVCOmax), the
value used for P must be large enough such that:
1.fVCOmax divided by P may not exceed the frequency
capability of fin (input to the ÷ N and ÷ A counters).
2.The period of fVCO divided by P must be greater than the
sum of the times:
a. Propagation delay through the dual–modulus prescaler.
b. Prescaler setup or release time relative to its MC signal.
c. Propagation time from fin to the MC output for the
frequency synthesizer device.
A sometimes useful simplification in the programming code
can be achieved by choosing the values for P of 8, 16, 32, or
64. For these cases, the desired value of NTresults when NT
in binary is used as the program code to the ÷ N and ÷ A coun-
ters treated in the following manner:
1.Assume the ÷A counter contains “a” bits where 2a≥P.
2.Always program all higher order ÷A counter bits above
“a” to 0.
Table 1. Partial List of Crystal Manufacturers
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE: Lansdale and Motorola do not recommend one supplier over another and in no
way suggests that this is a complete listing of crystal manufacturers.
ML12009
ML12011
ML12013
ML12015
ML12016
ML12017
ML12018
MC12028A
ML12052
ML12054A
÷ 5/÷ 6
÷ 8/÷ 9
÷ 10/÷ 11
÷ 32/÷ 33
÷ 40/÷ 41
÷ 64/÷ 65
÷ 128/÷ 129
÷ 32/33 or ÷ 64/65
÷ 64/65 or ÷ 128/129
÷ 64/65 or ÷ 128/129
440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
MC12034 ÷32/33 or ÷64/65
÷127/128 or ÷255/256
2.0 GHz
MC120381.1 GHz
1.1 GHz
2.0 GHz
NT=frequency into the prescaler
frequency into the phase detector = N • P + A
www.lansdale.comPage 31 of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
3. Assume the ÷N counter and the ÷A counter (with all the
higher order bits above “a” ignored) combined into a single
binary counter of n + a bits in length (n = number of divider
stages in the ÷N counter). The MSB of this “hypothetical”
counter is to correspond to the MSB of ÷ N and the LSB is to
correspond to the LSB of ÷ A. The system divide value, NT,
now results when the value of NTin binary is used to program
the “new” n + a bit counter.
By using the two devices, several dual–modulus values are
achievable (shown in Figure 13).
MC
DEVICE B
DEVICE A
DEVICE
BML12009 ML12011 ML12013DEVICE A
MC10131
MC10138
÷
20/
÷
21
÷
50/
÷
51
÷
32/
÷
33
÷
80/
÷
81
÷
40/
÷
41
÷
100/
÷
101
NOTE: ML12009, ML12011, and ML12013 are pin equivalent.
ML12015, ML12016, and ML12017 are pin equivalent.
Figure 13. Dual–Modulus Values
www.lansdale.comPage 32 of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 16 = EP
PLASTIC DIP
CASE 648–08
(ML145157EP, ML145158EP)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
H
GD
J
L
M
16 PL
SEATING
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.0080.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0° 10° 0° 10°
S0.020 0.040 0.51 1.01
P DIP 18 = VP
PLASTIC DIP
CASE 707–02
(ML145155VP)
MIN MINMAX MAX
MILLIMETERSINCHES
DIM
22.22
6.10
3.56
0.36
1.27
1.02
0.20
2.92
23.24
6.60
4.57
0.56
1.78
1.52
0.30
3.43
0°
0.51
0.875
0.240
0.140
0.014
0.050
0.040
0.008
0.115
0.915
0.260
0.180
0.022
0.070
0.060
0.012
0.135
15°
1.02
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
0°
0.020
15°
0.040
A
B
C
D
F
G
H
J
K
L
M
N
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
1018
B
A
H
F
G
D
SEATING
PLANE
NK
MJ
L
C
www.lansdale.comPage 33 of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
P DIP 20 = RP
PLASTIC DIP
CASE 738–03
(ML145156RP)
1.070
0.260
0.180
0.022
0.070
0.015
0.140
15°
0.040
1.010
0.240
0.150
0.015
0.050
0.008
0.110
0°
0.020
25.66
6.10
3.81
0.39
1.27
0.21
2.80
0°
0.51
27.17
6.60
4.57
0.55
1.77
0.38
3.55
15°
1.01
0.050 BSC
0.100 BSC
0.300 BSC
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHESMILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
-A-
C
K
N
E
GF
D 20 PL
J 20 PL
L
M
-T-
SEATING
PLANE
110
1120
0.25 (0.010) T A
M M
0.25 (0.010) T B
M M
B
SOG 20 = -6P
SOG PACKAGE
CASE 751D–04
(MC145155-6P, MC145156-6P)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOW ABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18XK
C
–T–
SEATING
PLANE
M
RX 45°
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A12.65 12.95 0.499 0.510
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.50 0.90 0.020 0.035
G1.27 BSC 0.050 BSC
J0.25 0.32 0.010 0.012
K0.10 0.25 0.004 0.009
M0° 7° 0° 7°
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
OUTLINE DIMENSIONS
www.lansdale.comPage 34 of 35 Issue A
ML1451xx
LANSDALE Semiconductor, Inc.
P DIP 28 = YP
OUTLINE DIMENSIONS
PLASTIC DIP
CASE 710–02
(ML145151YP, ML145152YP)
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
36.45
13.72
3.94
0.36
1.02
1.65
0.20
2.92
0
°
0.51
37.21
14.22
5.08
0.56
1.52
2.16
0.38
3.43
15
°
1.02
1.435
0.540
0.155
0.014
0.040
0.065
0.008
0.115
0
°
0.020
1.465
0.560
0.200
0.022
0.060
0.085
0.015
0.135
15
°
0.040
A
B
C
D
F
G
H
J
K
L
M
N
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
114
1528
B
AC
N
KMJ
D
SEATING
PLANE
F
HG
L
SO 28W = -6P
SOG PACKAGE
CASE 751F–04
(ML145151-6P, ML145152–6P)
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
17.80
7.40
2.35
0.35
0.41
0.23
0.13
0
°
10.05
0.25
18.05
7.60
2.65
0.49
0.90
0.32
0.29
8
°
10.55
0.75
0.701
0.292
0.093
0.014
0.016
0.009
0.005
0
°
0.395
0.010
0.711
0.299
0.104
0.019
0.035
0.013
0.011
8
°
0.415
0.029
1.27 BSC0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
-A-
-B-
114
1528
-T- C
SEATING
PLANE
0.010 (0.25) B
M M
M
J
-T-
K
26X G
28X D
14X P
RX 45°
F
0.010 (0.25) T A B
MS S
www.lansdale.comPage 35 of 35 Issue A
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. ÒTypical ”parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals”must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
ML1451xx
LANSDALE Semiconductor, Inc.
SOG 20 = -5P
SOG PACKAGE
CASE 751G–02
(ML145157-5P, ML145158-5P)
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A10.15 10.45 0.400 0.411
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.50 0.90 0.020 0.035
G1.27 BSC 0.050 BSC
J0.25 0.32 0.010 0.012
K0.10 0.25 0.004 0.009
M0° 7°
7°
0°
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
M
B
M
0.010 (0.25)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOW ABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P8X
G14X
D16X
SEATING
PLANE
–T–
S
A
M
0.010 (0.25) B S
T
16 9
81
F
J
RX 45°
M
C
K
OUTLINE DIMENSIONS
