©2001 Silicon Storage T echnology, Inc.
S71152-02-000 5/01 502
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MTP is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)
Many-Time Programmable Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
FEATURES:
• Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8
• 4.5-5.5V Read Operation
• Superior Reliability
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
•Low Power Consumption
–Active Current: 20 mA (typical)
–Standby Current: 10 µA (typical)
•Fast Read Access Time
–70 ns
–90 ns
•Fast Byte-Program Operation
–Byte-Program Time: 20 µs (typical)
–Chip Program Time:
0.7 seconds (typical) for SST27SF256
1.4 seconds (typical) for SST27SF512
2.8 seconds (typical) for SST27SF010
5.6 seconds (typical) for SST27SF020
•Electrical Erase Using Programmer
–Does not require UV source
–Chip-Erase Time: 100 ms (typical)
•TTL I/O Compatibility
•JEDEC Standard Byte-wide EPROM Pinouts
•Packages A vailable
–32-pin PLCC
–32-pin TSOP (8mm x 14mm)
–28-pin PDIP for SST27SF256/512
–32-pin PDIP for SST27SF010/020
PRODUCT DESCRIPTION
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 /
128K x8 / 256K x8 CMOS, Many-Time Programmable
(MTP) low cost flash, m an ufactured wi th SS T’s proprietary,
high performance SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. These MTP devices can be electrically erased
and programmed at least 1000 times using an e xternal pro-
grammer with a 12 volt power supply. They have to be
erased prior to programming. These devices conform to
JEDE C standa rd pino uts f or b yte -wide memories .
Featuring high performance Byte-Program, the
SST27SF256/512/010/020 provide a Byte-Progr am time of
20 µs. Designed, manufactured, and tested for a wide
spectrum of applications, these devices are offered with an
endurance of at least 1000 cycl es . Data retention is rated at
gr eat er t han 10 0 y e ar s.
The SS T27SF256 /512/010/020 are sui ted for appl ications
that require infrequent writes and low power nonvolatile
storage. These devices will improve flexibility, efficiency,
and perf ormance while matching the low cost in nonv olatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.
To meet surface mount and conventional through hole
requirements, the SST27SF256/512 are offered in 32-pin
PLCC, 32-pin TSOP, and 28-pin PDIP packages. The
SST2 7SF 010/0 20 a re of f e red in 32 -pin PDI P, 32 -pi n PLCC
and 32-pin TSOP packages. See Figures 1, 2, and 3 for
pinouts.
Device Operation
The SST27SF256/512/010/020 are a low cost flash solu-
tion that can be used to replace e xisting UV-EPROM, O TP,
and mask ROM sockets. These devices are functionally
(read an d program ) an d pin c om pat ible w ith i nd us try s ta n-
dard EPROM products. In addition to EPROM functionality,
these devices also support electrical erase operation via an
external programmer. They do not require a UV source to
erase, and therefore the packages do not have a window .
Read
The Read operation of the SST27SF256/512/010/020 is
controlled by CE# and OE#. Both CE# and OE# hav e to be
low for the system to obtain data from the outputs. Once
the addr ess is stable, the addres s acces s time i s equal t o
the delay from CE# to output (TCE). Data is available at the
output after a delay of TOE from the falling edge of OE#,
assuming that CE# pin has been low and the addresses
have been stable for at least TCE - TOE. When the CE# pin
is high, the chip is deselected and a typical standby current
of 10 µA is consumed. OE# is the output control and is
used to gat e data from the output pi ns. The data bus is in
high impedance state when either CE# or OE# is high.
Byte -Prog ram Oper a ti o n
The SS T27SF 256/ 512/0 10/020 are programmed by using
an external programmer. The programming mode for
SST27SF256/010/020 is activated by asserting 12V (±5%)
SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories
2
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
on VPP pin, VDD = 5V (±5%), VIL on CE# pin, and VIH on
OE# pin. The programming mode for SST27SF512 is acti-
vated by asser ting 12 V (±5%) on O E#/VPP pin, VDD = 5V
(±5%), and VIL on CE# pin. These devices are pro-
grammed byte-by-byte with the desired data at the desired
address using a single pulse (CE# pin low for
SST27SF256/512 and PGM# pin low for SST27SF010/
020) o f 2 0 µ s. Using the MTP program ming al go rithm, the
Byte-Programming process continues byte-by-byte until
the entire chip has been programmed.
Chip-Erase Operation
The only wa y to change a data from a “0” to “1” is b y el ectri-
cal erase that changes ev ery bit in the device to “1”. Unlike
traditional EPROMs, which use UV light to do the Chip-
Erase, the SST27SF256/512/010/020 uses an electrical
Chip-Erase operation. This saves a significant amount of
time (about 30 minutes for each Erase operation). The
entire chip can be erased in a single pulse of 100 ms (CE#
pin low for SST27SF256/512 and PGM# pin for
SST27SF010/020). In order to activate the Erase mode for
SST27SF256/010/020, the 12V (±5%) is applied to VPP
and A9 pins, VDD = 5V (±5%), VIL on CE# p in, a nd VIH on
OE# pi n. In orde r to activ ate Er ase mode f or SST 27SF512,
the 12V (±5%) is applied to OE#/VPP and A9 pins, VDD =
5V (±5% ), a nd V IL on CE # p in. All ot her a ddr e ss a nd data
pins are “don’t care”. The falling edge of CE# (PGM# for
SST27SF010/020) will start the Chip-Erase operation.
Once t he ch ip ha s be en erase d, all bytes must be ver ified
fo r FFH. Refer to Figures 13, 14, and 15 for the flowcharts.
Product Identification Mode
The Product Identification mode identifies the devices as
the SST27SF256, SST27SF512, SST27SF010 and
SST27SF020 and manufacturer as SST. This mode may
be accessed by the hardware method. To activate this
mode for SST27SF256/010/020, the programming equip-
ment must force VH (12V±5%) on address A9 with VPP pin
at VDD (5V±10%) or VSS. To activate this mode for
SST27 SF512 , the p rogrammin g equi pmen t must force VH
(12V±5%) on address A9 with OE#/VPP pin at VIL. Two
identifier bytes may then be sequenced from the device
outputs by toggling address line A0. F or details, see Tables
3, 4, and 5 f or hardware operation.
TABLE 1: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST27SF256 0001H A3H
SST27SF512 0001H A4H
SST27SF010 0001H A5H
SST27SF020 0001H A6H
T1.1 502
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
3
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
Y-Decoder
I/O Buffers
502 ILL B1.1
Address Buffer
X-Decoder
DQ7 - DQ0
A14 - A0
A9
OE#
CE#
VPP
SuperFlash
Memory
Control Logic
FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF256
Y-Decoder
I/O Buffers
502 ILL B2.1
Address Buffer
X-Decoder
DQ7 - DQ0
A15 - A0
A9
OE#/VPP
CE#
SuperFlash
Memory
Control Logic
FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF512
Y-Decoder
I/O Buffers
502 ILL B3.2
Address Buffer
X-Decoder
DQ7 - DQ0
AMS - A0
A9
OE#
CE#
SuperFlash
Memory
Control Logic
PGM#
VPP
AMS = A17 for SST27SF020, A16 for SST27SF010
FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF010/020
4
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC
502 ILL F02c.2
SST27SF256SST27SF512 SST27SF512SST27SF010 SST27SF010SST27SF020 SST27SF020SST27SF256
SST27SF256SST27SF512 SST27SF512SST27SF010 SST27SF010SST27SF020 SST27SF020SST27SF256
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A8
A9
A11
NC
OE#
A10
CE#
DQ7
DQ6
A8
A9
A11
NC
OE#/VPP
A10
CE#
DQ7
DQ6
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
4 3 2 1 32 31 30
A7
A12
VPP
NC
VDD
A14
A13
A7
A12
A15
NC
VDD
A14
A13
A12
A15
A16
VPP
VDD
PGM#
NC
A12
A15
A16
VPP
VDD
PGM#
A17
32-pin PLCC
Top View
14 15 16 17 18 19 20
DQ1
DQ2
VSS
NC
DQ3
DQ4
DQ5
DQ1
DQ2
VSS
NC
DQ3
DQ4
DQ5
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
5
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)
FIGURE 3: PIN ASSIGNMENTS FOR 28-PIN AND 32-PIN PDIP
502 ILL F01.1
A11
A9
A8
A13
A14
NC
NC
VDD
VPP
NC
NC
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
NC
VDD
NC
NC
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
PGM#
VDD
VPP
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
PGM#
VDD
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#/VPP
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Standard Pinout
Top View
Die Up
SST27SF256SST27SF512 SST27SF512SST27SF010 SST27SF010SST27SF020 SST27SF020SST27SF256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
PDIP
Top View
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
PGM#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
PGM#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
502 ILL F02b.1
SST27SF010 SST27SF010SST27SF020 SST27SF020
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin
PDIP
Top View
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
A14
A13
A8
A9
A11
OE#/VPP
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
502 ILL F02a.1
SST27SF512SST27SF256SST27SF512 SST27SF256
6
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
TABLE 2: PIN DESCRIPTION
Symbol Pin Name Functions
AMS1-A0Address Inputs To provide memory addresses
DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Program cycles
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low
OE# Output Enable For SST27SF256/010/020, to gate the data output buffers during Read operation
OE#/VPP Output Enable/ VPP For SST27 SF512, to ga te the data ou tput b uff ers during Read oper a tion and high v oltage
pin during Chip-Erase and programming operation
VPP Power Supply for
Program or Erase For SST27SF256/010/020, high voltage pin during Chip-Erase and programming opera-
tion 12V (±5%)
VDD Power Supply To provide 5.0V supply (±10%)
VSS Ground
NC No Connection Unconnected pins.
T2.3 502
1. AMS = Most significant address
AMS = A14 for SST27SF256, A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
7
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
Note: X = VIL or VIH
VPPH = 12V±5%, VH = 12V ±5%
Note: X = VIL or VIH
VPPH = 12V±5%, VH = 12V ±5%
TABLE 3: OPERATION MODES SELECTION FOR SS T2 7SF256
Mode CE# OE# VPP A9DQ Address
Read VIL VIL VDD or VSS AIN DOUT AIN
Output Disable VIL VIH VDD or VSS XHigh Z X
Byte-Program VIL VIH VPPH AIN DIN AIN
Standby VIH XV
DD or VSS XHigh Z X
Chip-Erase VIL VIH VPPH VHHigh Z X
Program/Eras e Inhibit VIH XV
PPH XHigh Z X
Product Identification VIL VIL VDD or VSS VHManufacturer’s ID (BFH)
De vic e ID (A3H) A14 - A1 = VIL, A0 = VIL
A14 - A1 = VIL, A0 = VIH
T3.1 502
TABLE 4: OPERATION MODES SELECTION FOR SS T2 7SF512
Mode CE# OE#/VPP A9DQ Address
Read VIL VIL AIN DOUT AIN
Output Disable VIL VIH X High Z X
Program VIL VPPH AIN DIN AIN
Standby VIH X X High Z X
Chip-Erase VIL VPPH VHHigh Z X
Program/Eras e Inhibit VIH VPPH X High Z X
Product Identification VIL VIL VHManufacturer’s ID (BFH)
Device ID (A4H) A15 - A1 = VIL, A0 = VIL
A15 - A1 = VIL, A0 = VIH
T4.1 502
TABLE 5: OPERATION MODES SELECTION FOR SS T2 7SF010/02 0
Mode CE# OE# PGM# A9VPP DQ Address
Read VIL VIL XA
IN VDD or VSS DOUT AIN
Output Disable VIL VIH XXV
DD or VSS High Z AIN
Program VIL VIH VIL AIN VPPH DIN AIN
Standby VIH XXXV
DD or VSS High Z X
Chip-Erase VIL VIH VIL VHVPPH High Z X
Program/Eras e Inhibit VIH XXXV
PPH High Z X
Product Identification VIL VIL XV
HVDD or VSS Manufacturer’s ID (BFH)
Device ID1
1. Device ID = A5H for SST27SF010 and A6H for SST27SF020
AMS2 - A1 = VIL, A0 = VIL
AMS2 - A1 = VIL, A0 = VIH
2. AMS = Most significant address
AMS = A16 for SST27SF010 and A17 for SST27SF020
Note: X = VIL or VIH
VPPH = 12V±5%, VH = 12V ±5%
T5.1 502
8
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent da mage to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C . Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to VDD+1.0V
Voltage on A9 and VPP Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Cur rent1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Outputs shor ted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Ambient Temp VDD VPP
Commercial 0°C to +70°C5.0V±10%12V±5%
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . CL = 100 pF for 90 ns
Output Load . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns
See Figures 11 and 12
TABLE 6: READ MODE DC OPERATING CHARACTERISTICS FOR S ST27SF 256 /512/010/0 20
VDD = 5.0V±10%, VPP=VDD OR VSS (Ta = 0°C to +70°C (Commercial))
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD VDD Read Current Address input=VIL/VIH at f=1/TRC Min
VDD=VDD Max
30 mA CE#=OE#=VIL, all I/Os open
IPPR VPP Read Current Address input=VIL/VIH at f=1/TRC Min
VDD=VDD Max, VPP=VDD
100 µA CE#=OE#=VIL, all I/Os open
ISB1 Standby VDD Current
(TTL input) 3mACE#=V
IH, VDD=VDD Max
ISB2 Standby VDD Current
(CMOS input) 100 µA CE#=VDD-0.3
VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Ma x
ILO Output Lea ka ge Cu rren t 10 µA VOUT=GND to VDD, VDD=VDD Ma x
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 2.0 VDD+0.5 V VDD=VDD Max
VOL O utput Lo w Voltage 0.2 V IOL=2.1 mA, VDD=VDD Min
VOH O ut put H igh Voltage 2.4 V IOH=-400 µA, VDD=VDD Min
IHSupervoltage Current for A9100 µA CE#=OE#=VIL, A9=VH Max
T6.3 502
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
9
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
TABLE 7: PROGRAM/ERASE DC OPERATING CHARACTERISTICS FOR SST27SF25 6
VDD=5.0V±10%, VPP=VPPH (Ta= 25°C±5°C)
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD VDD Erase or Program Current 30 mA CE#=VIL, OE#=VIH, VPP=12V±5%, VDD=VDD Max
IPP VPP Erase or Program Current 1 mA CE#=VIL, OE#=VIH, VPP=12V±5%, VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max
VHSupervoltage for A911.4 12.6 V CE#=OE#=VIL,
IHSupervoltage Current for A9100 µA CE#=OE#=VIL, A9=VH Max
VPPH High Voltage for VPP Pin 11.4 12.6 V
T7.1 502
TABLE 8: PROGRAM/ERASE DC OPERATING CHARACTERISTICS FOR SST27SF51 2
VDD=5.0V±10%, VPP=VPPH (Ta= 25°C±5°C)
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD VDD Erase or Program Current 30 mA CE#=VIL, OE#/VPP=12V±5%, VDD=VDD Max
IPP VPP Erase or Program Current 1 mA CE#=VIL, OE#/VPP=12V±5%, VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max
VHSupervoltage for A911.4 12.6 V CE#=OE#/VPP=VIL,
IHSupervoltage Current for A9100 µA CE#=OE#/VPP=VIL, A9=VH Max
VPPH High Voltage for OE#/VPP Pin 11.4 12.6 V
T8.1 502
TABLE 9: PROGRAM/ERASE DC OPERATING CHARACTERISTICS FOR SST27SF01 0/020
VDD=5.0V±10%, VPP=VPPH (Ta= 25°C±5°C)
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD VDD Erase or Program Current 30 mA CE#=PGM#=VIL, OE#=VIH, VPP=12V±5%,
VDD=VDD Max
IPP VPP Erase or Program Current 1 mA CE#=PGM#=VIL, OE#=VIH, VPP=12V±5%,
VDD=VDD Max
ILI Input Leakage Current 1 µA VIN =GND to VDD, VDD=VDD Max
ILO Output Leakage Current 1 µA VOUT =GND to VDD, VDD=VDD Max
VHSupervoltage for A911.4 12.6 V CE#=OE#=VIL,
IHSupervoltage Current for A9100 µA CE#=OE#=VIL, A9=VH Max
VPPH High Voltage for VPP Pin 11.4 12.6 V
T9.1 502
10
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
AC CHARACTERISTICS
TABLE 10: RECOMMENDED SYSTEM POWER-UP T IMINGS
Symbol Parameter Minimum Units
TPU-READ1Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Write Operation 100 µs
T10.1 502
1. This parameter is measured only f or initial qualif ication and after a design or process change that could affect this parameter.
TABLE 11: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins ope n)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only f or initial qualif ication and after a design or process change that could affect this parameter.
I/O Pin Capacitance VI/O = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
T11.0 502
TABLE 12: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1
1. This parameter is measured only f or initial qualif ication and after a design or process change that could affect this parameter.
Endurance 1000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 mA JEDEC Standard 78
T12.2 502
TABLE 13: READ CYCLE TIMING PARAMETERS VDD = 5.0V±10% (Ta = 0°C to +70°C ( C om m e rcial))
Symbol Parameter
SST27SF256-70
SST27SF512-70
SST27SF010-70
SST27SF020-70
SST27SF256-90
SST27SF512-90
SST27SF010-90
SST27SF020-90
UnitsMinMaxMinMax
TRC Read Cyc le Tim e 70 90 ns
TCE Chip Enable Access Time 70 90 ns
TAA Address Access Time 70 90 ns
TOE Output Enable Access Time 35 45 ns
TCLZ1
1. This parameter is measured only f or initial qualif ication and after a design or process change that could affect this parameter.
CE# Low to Active Output 0 0 ns
TOLZ1OE# Low to Active Output 0 0 ns
TCHZ1CE# High to High-Z Output 25 30 ns
TOHZ1OE# High to High-Z Output 25 30 ns
TOH1Output Hold from Address Change 0 0 ns
T13.1 502
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
11
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR S ST27SF 256
Symbol Parameter Min Max Units
TAS Address Setup Time 1 µs
TAH Address Hold Time 1 µs
TPRT VPP Pulse Rise Time 50 ns
TVPS VPP Setup Time 1 µs
TVPH VPP Hold Time 1 µs
TPW CE# Program Pulse Width 20 30 µs
TEW CE# Erase Puls e Wid th 100 500 ms
TDS Data Setup Time 1 µs
TDH Data Hold Time 1 µs
TVR VPP and A9 Recovery Time 1 µs
TART A9 Rise Time to 12V during Erase 50 ns
TA9S A9 Setup Time during Erase 1 µs
TA9H A9 Hold Time during Erase 1 µs
T14.0 502
TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR S ST27SF 512
Symbol Parameter Min Max Units
TAS Address Setup Time 1 µs
TAH Address Hold Time 1 µs
TPRT OE#/VPP Pulse Rise Time 50 ns
TVPS OE#/VPP Setup Time 1 µs
TVPH OE#/VPP Hold Time 1 µs
TPW CE# Program Pulse Width 20 30 µs
TEW CE# Erase Puls e Wid th 100 500 ms
TDS Data Setup Time 1 µs
TDH Data Hold Time 1 µs
TVR OE#/VPP and A9 Recove ry Time 1 µs
TART A9 Rise Time to 12V during Erase 50 ns
TA9S A9 Setup Time during Erase 1 µs
TA9H A9 Hold Time during Erase 1 µs
T15.0 502
TABLE 16: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR S ST27SF 010 /020
Symbol Parameter Min Max Units
TCES CE# Setup Time 1 µs
TCEH CE# Hold Time 1 µs
TAS Address Setup Time 1 µs
TAH Address Hold Time 1 µs
TPRT VPP Pulse Rise Time 50 ns
TVPS VPP Setup Time 1 µs
TVPH VPP Hold Time 1 µs
TPW PGM# Program Pulse Width 20 30 µs
TEW PGM# Erase Pulse Width 100 500 ms
TDS Data Setup Time 1 µs
TDH Data Hold Time 1 µs
TVR A9 Recovery Time for Erase 1 µs
TART A9 Rise Time to 12V during Erase 50 ns
TA9S A9 Setup Time during Erase 1 µs
TA9H A9 Hold Time during Erase 1 µs
T16.0 502
12
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 4: READ CYCLE TIMING DIAGRAM FOR SST27SF256/512 /010/020
FIGURE 5: CHIP-ERASE TIMING DIAGRAM FOR SST 27SF 256
502 ILL F03.0
D ATA V ALIDD ATA V ALID
TCLZ
TOLZ
TOH
TRC TAA
TOE TOHZ
TCHZ
HIGH-Z
DQ7-0
OE#
CE#
ADDRESS
TCE
502 ILL F04a.1
TA9H
TVR
TVPH
TVPS
TEW
TPRT
VDD
VSS
VPP
A9
VPPH
VPPH
VIH
VIH
VIL
DQ7-0
CE#
OE#
ADDRESS
(EXCEPT A9)
TA9S
TART
TVR
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
13
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 6: READ CYCLE TIMING DIAGRAM FOR SST27SF512
FIGURE 7: CHIP-ERASE TIMING DIAGRAM FOR SST 27SF 010/020
502 ILL F04b.1
TA9H
TVR
TVPH
TVPS
TEW
TPRT
VDD
VSS
OE#/VPP
A9
VPPH
VPPH
VIH
VIL
DQ7-0
CE#
ADDRESS
(EXCEPT A9)
TA9S
TART
TVR
502 ILL F04c.1
TA9H
TVR
TVPH
TVPS
TCEH
TPRT
VDD
VSS
VPP
A9
PGM#
VPPH
VPPH
VIH
VIH
VIL
DQ7-0
OE#
CE#
ADDRESS
(EXCEPT A9)
TA9S
TART
TCES
TEW
14
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 8: BYTE-PROGRAM TIMING DIAGRAM FOR SST27SF 256
FIGURE 9: BYTE-PROGRAM TIMING DIAGRAM FOR SST27SF 512
502 ILL F05a.1
D ATA V ALID
ADDRESS V ALID
TAH
TPW
TDH
TAS
TDS
TVR
VDD
VPPH
VIH
HIGH-Z
VSS TVPH
TPRT
TVPS
VPP
DQ7-0
CE#
OE#
ADDRESS
502 ILL F05b.2
D ATA V ALID
ADDRESS V ALID
TAH
TPW
TDH
TAS
TDS
TVR
VDD
VPPH
HIGH-Z
VSS
TVPH
TPRT
TVPS
OE#/VPP
DQ7-0
CE#
ADDRESS
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
15
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 10: BYTE-PROGRAM TIMING DIAGRAM FOR SST27SF 010/0 20
502 ILL F05c.1
D ATA V ALID
ADDRESS V ALID
TAH
TCEH
TAS
TDS TDH
VDD
VPPH
HIGH-Z
VIH
VSS
TCES
TPW TVPH
TPRT
TVPS
VPP
PGM#
DQ7-0
OE#
CE#
ADDRESS
16
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 11: AC I NPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 12: A TEST LOAD EXAMPLE
502 ILL F06.0
REFERENCE POINTS OUTPUTINPUT
VHT
VLT
VHT
VLT
VIHT
VILT
AC test inpu ts ar e dr i ven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V ) for a logic “0”. Measurement r eference poi nt s for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
502 ILL F07.1
T O TESTER
TO DUT
CLRL LOW
RL HIGH
VDD
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
17
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 13: CHIP-ERASE ALGORITHM FOR SST27SF 256
Start
VPP = VPPH, A9 = VH
VPP = VDD or VSS
A9 = VIL or VIH
Wait for VPP and A9
Recov ery Time
Erase 100ms pulse
(CE# = VIL)
Read Device
(CE# = OE# = VIL)
Device Passed
Compare All
bytes to FFH
Device Failed
502 ILL F08a.2
No
Yes
18
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 14: CHIP-ERASE ALGORITHM FOR SST27SF 512
OE#/VPP = VPPH
OE#/VPP = VDD or VSS
A9 = VIL or VIH
Wait for OE#/VPP and
A9 Recovery Time
Erase 100ms pulse
(CE# = VIL)
Read Device
(CE# = OE# = VIL)
Device Passed
Compare All
bytes to FFH
Device Failed
502 ILL F08b.2
Start
A9 = VH
No
Yes
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
19
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 15: CHIP-ERASE ALGORITHM FOR SST27SF 010/020
Start
A9 = VH, VPP = VPPH
A9 = VIL or VIH
CE# = VIL, OE# = VIH
Wait A9 Recovery Time
Erase 100ms pulse
(PGM# = VIL)
Read Device
Device Passed
Compare all
bytes to FFH
Device Failed
502 ILL F08c.1
PGM# = VIH
No
Yes
20
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 16: BYTE-PROGRAM ALGORITHM FOR SST27SF 256
Start
Erase*
VPP = VPPH
Address = First Location
Program 20µs pulse
(CE# = VIL)
Read Device
(CE# = OE# = VIL)
Device Passed
Compare all bytes
to original data
Increment Address
Device Failed
502 ILL F09a.3
Last Address?
Wait for VPP
RecoveryTime
VPP = VDD or VSS
No
No
Yes
Yes
* See Figure 13
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
21
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 17: BYTE-PROGRAM ALGORITHM FOR SST27SF 512
Start
Erase*
OE#/VPP = VPPH
Address = First Location
Program 20µs pulse
(CE# = VIL)
Read Device
(CE# = OE# = VIL)
Device Passed
Compare all bytes
to original data
Increment Address
Device Failed
502 ILL F09b.2
Last Address?
Wait for OE#/VPP
RecoveryTime
OE#/VPP = VDD or VSS
No
No
Yes
Yes
* See Figure 14
22
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
FIGURE 18: BYTE-PROGRAM ALGORITHM FOR SST27SF 010/02 0
Start
Erase*
VPP = VPPH
Address = First Location
CE# = VIL, OE# = VIH
Program 20µs pulse
(PGM# = VIL)
Read Device
Device Passed
Compare all bytes
to original data
Increment Address
Device Failed
502 ILL F09c.1
Last Address?
No
No
Yes
Yes
* See Figure 15
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
23
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
Device Speed Suffix1 Suffix2
SST27SFxxx -XXX -XX-XX
Package M o di f i e r
G = 28 pins
H = 32 pins
Numeric = Die modifier
Package Typ e
N = PLCC
W = TSOP (die up) (8mm x 14mm)
P = PDIP
Operating Temperature
C = Commercial = 0° to +70°C
Minimum Endurance
3 = 1000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Device Density
256 = 256 Kilobit
512 = 512 Kilobit
010 = 1 Megabi t
020 = 2 Megabi t
24
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
Valid combinations for SST27SF256
SST27SF256-70-3C-NH SST27SF256-70-3C-WH SST27SF256-70-3C-PG
SST27SF256-90-3C-NH SST27SF256-90-3C-WH SST27SF256-90-3C-PG
Valid combinations for SST27SF512
SST27SF512-70-3C-NH SST27SF512-70-3C-WH SST27SF512-70-3C-PG
SST27SF512-90-3C-NH SST27SF512-90-3C-WH SST27SF512-90-3C-PG
Valid combinations for SST27SF010
SST27SF010-70-3C-NH SST27SF010-70-3C-WH SST27SF010-70-3C-PH
SST27SF010-90-3C-NH SST27SF010-90-3C-WH SST27SF010-90-3C-PH
Valid combinations for SST27SF020
SST27SF020-70-3C-NH SST27SF020-70-3C-WH SST27SF020-70-3C-PH
SST27SF020-90-3C-NH SST27SF020-90-3C-WH SST27SF020-90-3C-PH
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availabi lity of new combinations .
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
25
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
PACKAGING DIAGRAMS
32-PIN PLASTIC L EAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
32-PIN THIN SMALL OUTLINE PACKAGE (TSO P) 8MM X 14MM
SST PACKAGE CODE: WH
.030
.040
.013
.021 .490
.530
.075
.095
.015 Min.
.125
.140
T OP VIEW SIDE VIEW BO TT OM VIEW
1232
.026
.032
.400
BSC
32.PLCC.NH-ILL.2
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
.050
BSC.
.050
BSC.
.026
.032
.023
.029
.447
.453
.042
.048
.042
.048
Optional
Pin #1 Identifier
.547
.553
.585
.595
.485
.495
.020 R.
MAX.
.106
.112
R.
x 30˚
32.TSOP-WH-ILL.4
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
8.10
7.90
.270
.170
1.05
0.95
.50
BSC
0.15
0.05
12.50
12.30
Pin # 1 Identifier
14.20
13.80
0.70
0.50
26
Data Sheet
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
©2001 Silicon Storage Technology, Inc. S71152-02-000 5/01 502
28-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PG
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)
SST PACKAGE CODE: PH
28.pdipPG-ILL.2
Pin #1 Identifier
C
L
28
1
Base Plane
Seating Plane
Note: 1. Complies with JEDEC publication 95 MO-015 AH dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
.170
.200
7˚
4 PLCS.
.600 BSC
.100 BSC
.120
.150
.016
.022
.045
.065
.070
.080
.015
.050
.065
.075 1.445
1.455
.008
.012
0˚
15˚
.600
.625
.530
.550
32.pdipPH-ILL.2
Pin #1 Identifier
C
L
32
1
Base Plane
Seating Plane
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
.170
.200
7˚
4 PLCS.
.600 BSC
.100 BSC
.120
.150
.016
.022
.045
.065
.070
.080
.015
.050
.065
.075 1.645
1.655
.008
.012
0˚
15˚
.600
.625
.530
.550
Silicon Storage Technology, Inc. • 117 1 Sonora Court • Sunnyvale , CA 940 86 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
